Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
16.7.5.2 D7:D6 - PLL Clock Scale Bits
These bits scale the clock source to the SPI Baud Rate Generator when the BRG clock source is the
PLL. These bits only apply when CLKSRC bit in the SPI Clock Control Register is set to '1' for the PLL.
The D7 and D6 are ignored when CLKSRC is deasserted '0'. See Section 16.5.1, "Full Duplex Mode"
for information and supported frequencies.
Table 16.10 SPI Baud Rate Generator Clock Sources
D7 (SPICS1)
D6 (SPICS0)
CLOCK
0
0
1
1
0
1
0
1
4 MHz
8 MHz
12 MHz
Reserved
16.8
16.9
SPIDONE - 8051 Interrupt
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SPIDONE interrupt is in Wakeup Source Register 7 and Wakeup Mask Register 7. See Table 7.25
on page 73, Table 7.32 on page 77, and Figure 7.4 on page 65.
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The SPIDONE interrupt notifies the 8051 MCU that the SPI interrupt has completed an 8-bit serial
transaction. The SPIDONE interrupt is asserted whenever the SPINT (internal signal) goes from '0'
to '1' at the end of SPI cycle. The SPINT is a pulse that is generated at the end of every SPI cycle
(when the internal nBUSY signal goes from '0' to '1' - see Section 16.7.2.1, "D0 - nBUSY (Status)").
Writing a '1' to the SPIDONE clears it. The SPIDONE interrupt also generates 8051 INT5. The
SPIDONE interrupt can be masked from generating 8051 INT5 (see Figure 7.4 on page 65) by using
the mask bit in Wakeup Mask Register 7.
SPI Timings
Refer to Section 29.8, "Serial Peripheral Interface (SPI) Timings," on page 301.
16.10 SPI Examples
16.10.1 Full Duplex Mode Transfer Examples
16.10.1.1 Read Only
The slave device used in this example is a MAXIM MAX1080 10 bit, 8 channel ADC:
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The MISC10 bit is '1' and SPIMODE bit is deasserted '0' to enable the SPI interface in Full Duplex
mode.
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The CLKPOL and TCLKPH bits are deasserted '0', and RCLKPH is asserted '1' to match the
clocking requirements of the slave device.
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The LSBF bit is deasserted '0' to indicate that the slave expects data in MSB-first order.
Assert #CS using a GPIO pin.
Write a valid command word (as specified by the slave device) to the SPI Data register (SPIDR)
with nBUSY deasserted '1'. The SPI master automatically clears the nBUSY bit, begins shifting the
data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled
on each clock.
SMSC LPC47N350
185
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
