Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
16.7.4 SPICC - SPI Clock Control Register
Table 16.7 SPI Clock Control Register (SPICC)
N/A
HOST ADDRESS
8051 ADDRESS
POWER
BEh
VCC1
00h on VCC1 POR
and when MISC10 bit
changes
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R/W
R/W
R/W
R/W
Reserved
RCLKPH CLKEN
CLKSRC CLKPOL TCLKPH
16.7.4.1 D0 - TCLKPH - Transmit Clock Phase
The TCLKPH bit determines the SPCLK edge on which the master will clock data out. When TCLKPH
is deasserted '0', valid data is clocked out on the SPDOUT signal prior to the first SPCLK edge. The
slave device should sample this data on the first and following odd SPCLK edges. When TCLKPH is
asserted '1', data on SPDOUT signal is clocked out on the first SPCLK edge. The slave device should
sample this data on the second and following even SPCLK edges. Note that this functionality is
independent of the polarity of SPCLK. See Section 16.9, "SPI Timings" for timing diagrams.
16.7.4.2 D1 - CLKPOL - SPI Clock Polarity
This bit controls the polarity of the SPI clock. When CLKPOL is deasserted '0', the SPCLK is low when
the interface is idle and the first clock edge is a rising edge. When CLKPOL is asserted '1', the first
clock edge is a falling edge and the SPCLK signal is high when the interface is idle. See Section 16.9,
"SPI Timings" for timing diagrams.
16.7.4.3 D2 - CLKSRC - SPI Clock Source
When CLKSRC is deasserted '0', the SPI is running from the Ring Oscillator. When CLKSRC is asserted
'1', the SPI is running from the PLL.
USER’S NOTE: The CLKSRC bit shouldn't be changed during SPI transaction.
16.7.4.4 D3 - CLKEN - Clock Enable
This bit enables the clock into the SPI logic. When CLKEN is deasserted '0', the clock source into the
SPI logic is disabled. When CLKEN is asserted '1', the clock source into the SPI logic is enabled.
16.7.4.5 D4 - RCLKPH - Receive Clock Phase
The RCLKPH bit determines the SPCLK edge on which the master will sample data. When RCLKPH is
deasserted '0', valid data is expected on the SPDIN signal on the first SPCLK edge. This data is
sampled on the first and following odd SPCLK edges. When RCLKPH is asserted '1', data on SPDIN
signal is expected after the first SPCLK edge. This data is sampled on the second and following even
SMSC LPC47N350
183
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
