Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
invalid since the last cycle was initiated solely to transmit command data to the slave. This particular
slave device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR
data is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, EEPROM address A15-A8 is written to the SPIDR. The SPI master automatically clears the
nBUSY bit, begins shifting the address value onto the SPDOUT pin, and drives the SPCLK pin. Data
on the SPDIN pin is also sampled on each clock. Note: The particular slave device ignores address
A15-A13.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit address to the slave. This particular slave
device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR data
is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, EEPROM address A17-A0 is written to the SPIDR. The SPI master automatically clears the
nBUSY bit, begins shifting the address value onto the SPDOUT pin, and drives the SPCLK pin. Data
on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit address to the slave. This particular slave
device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR data
is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, data bits D7-D0 is written to the SPIDR. The SPI master automatically clears the nBUSY bit,
begins shifting the address value onto the SPDOUT pin, and drives the SPCLK pin. Data on the
SPDIN pin is also sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit data to the slave. This particular slave
device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR data
is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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If no more data needs to be received by the master, CS# is released and the SPI is idle. Otherwise,
master continues writing data (up to max byte page allowed by the device) to the SPIDR after every
8 clock cycles.
16.10.2 Bidirectional Mode Transfer Example
The slave device used in this example is a National LM74 12 bit (plus sign) temperature sensor.
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The MISC10 bit is asserted '1' and the SPI interface is enabled.
The interface is configured for Bidirectional mode by asserting ('1') the SPIMODE bit.
The CLKPOL, TCLKPH and RCLKPH bits are deasserted '0' to match the clocking requirements of
the slave device.
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The LSBF bit is deasserted '0' to indicate that the slave expects data in MSB-first order.
BIOEN is asserted '0' to indicate that the first data in the transaction is to be received from the slave.
Assert #CS using a GPIO pin.
Write a dummy command byte to the SPI Data register (SPIDR) with nBUSY deasserted '1'. The
SPI master automatically clears the nBUSY bit, begins shifting the data value and driving the
SPCLK. This data is lost because the output buffer is disabled. Data on the SPDIN pin is sampled
on each clock.
Revision 1.1 (01-14-03)
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SMSC LPC47N350
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