Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR data
is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, EEPROM address A17-A0 is written to the SPIDR. The SPI master automatically clears the
nBUSY bit, begins shifting the address value onto the SPDOUT pin, and drives the SPCLK pin. Data
on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit address to the slave. This particular slave
device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR data
is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, a dummy 8 bit data value (any value) as written to the SPIDR. The SPI master automatically
clears the nBUSY bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the
SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted. The data now contained in SPIDR is the 8-bit EEPROM data. SPIDR is read and stored.
If more than 8-bit data needs to be read, another dummy 8 bit value is written to the SPIDR. The
SPI master automatically clears the nBUSY bit, begins shifting the dummy data value onto the
SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted. The data now contained in SPIDR is the second 8-bit EEPROM data. SPIDR is read and
stored.
If no more data needs to be received by the master, CS# is released and the SPI is idle. Otherwise,
master continues reading the data by writing a dummy value to the SPIDR after every 8 clock cycles.
Write
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The MISC10 bit is '1' and SPIMODE bit is deasserted '0' to enable the SPI interface in Full Duplex
mode.
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The CLKPOL, TCLKPH and RCLKPH bits are deasserted '0' to match the clocking requirements of
the slave device.
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The LSBF bit is deasserted '0' to indicate that the slave expects data in MSB-first order.
Assert WR# high using a GPIO pin.
Assert CS# low using a GPIO pin.
Write a valid write enable command word (as specified by the slave device) to the SPI Data register
(SPIDR) with nBUSY deasserted '1'. The SPI master automatically clears the nBUSY bit, begins
shifting the data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is
also sampled on each clock.
■
After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit write enable command to the slave. This
particular slave device tri-states the SPDIN pin to the master while it is accepting command data.
This SPIDR data is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
■
Write a valid write command word (as specified by the slave device) to the SPI Data register (SPIDR)
with nBUSY deasserted '1'. The SPI master automatically clears the nBUSY bit, begins shifting the
data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled
on each clock.
■
After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
SMSC LPC47N350
187
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
