Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
16.7.2 SPISR - SPI Status Register
Table 16.5 SPI Status Register (SPISR)
N/A
HOST ADDRESS
8051 ADDRESS
POWER
BCh
VCC1
01h on VCC1 POR
and when MISC10 bit
changes
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R
R
R
Reserved
nBUSY
16.7.2.1 D0 - nBUSY (Status)
The nBUSY bit reflects the state of the internal nBUSY signal. When nBUSY signal is asserted '0', a
SPI transfer is in progress and data should not be written to the SPI Data register (SPIDR). Any writes
to SPIDR while nBUSY signal is asserted will be ignored. When nBUSY signal is deasserted '1', a
transaction has completed and the 8-bit value contained in the SPIDR is data acquired during the last
transaction. Software must determine if the data contained in SPIDR is valid. New data may be written
to SPIDR to begin a new transaction. When the nBUSY signal goes from '0' to '1' at the end of an SPI
cycle, the 8051 SPIDONE interrupt is set (See Section 16.8, "SPIDONE - 8051 Interrupt"). See
Figure 16.3 for nBUSY signal and SPIDONE functionality.
Delay from previous transfer
cycle to next transfer cycle
(see Note)
SPIDR register
nBUSY is set low when SPIDR
register is written
Set high After 8
Clock Cycles
is written again
nBUSY
(internal signal)
SPCLK Pin
SPIDONE bit
Cleared by writing
'1' to the bit
Note: The delay is due to the read and/or write processing time of 8051 to the SPIDR register.
The next transfer cycle starts when the SPIDR register is written with nBUSY signal high and
regardless of when the SPIDONE bit is cleared. The clearing of SPIDONE bit is not controlled
by the SPI Block.
Figure 16.3 nBUSY and SPIDONE Functionality
SMSC LPC47N350
181
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
