Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is the
first half of the 16 bit word containing the temperature data. This SPIDR data is stored.
Next, another dummy 8 bit data value is written to the SPIDR. The SPI master automatically clears
the nBUSY bit, begins shifting the dummy data value and drives the SPCLK pin. Data on the SPDIN
pin is sampled on each clock. The last 3 bits of this byte are used as a bus turnaround. The
peripheral device sends '1' and tri-states its output for last two bits assuming that next data byte will
be driven by the master.
USER’S NOTE: External pull-up or pull-down is required if the SPDIN is tri-stated by the slave device.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted. The data now contained in SPIDR is the last half of the 16 bit word containing the
temperature data. SPIDR is read and stored.
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BIOEN is asserted '1' to indicate that data will now be driven by the master.
The next SPI cycle is initiated when another 8 bit data value is written to the SPIDR. This value is
the first half of a 16 bit command to be sent to temperature sensor peripheral. The SPI master
automatically clears the nBUSY bit, begins shifting the data value onto the SPDOUT pin, and drives
the SPCLK pin. Data on the SPDIN pin is sampled on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted. The data now contained in SPIDR is ignored.
The final SPI cycle is initiated when another 8 bit data value is written to the SPIDR. This value is
the second half of a 16 bit command to be sent to temperature sensor peripheral. The SPI master
automatically clears the nBUSY bit, begins shifting the data value onto the SPDOUT pin, and drives
the SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the final SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt
is asserted. The data now contained in SPIDR is ignored.
#CS is deasserted.
SMSC LPC47N350
189
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
