Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
SPCLK edges. Note that this functionality is independent of the polarity of SPCLK. See Section 16.9,
"SPI Timings" for timing diagrams.
16.7.5 SPIBR - SPI Baud Rate Register
Table 16.8 SPI Baud Rate Register (SPIBR)
N/A
HOST ADDRESS
8051 ADDRESS
POWER
BFh
VCC1
00h on VCC1 POR
and when MISC10 bit
changes
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R/W
R/W
R
R
R
R/W
R/W
R/W
SPICS1
SPICS0
Reserved
SPICD2
SPICD1
SPICD0
16.7.5.1 D2:D0 - SPI Clock Divider Bits
The clock divider bits (SPICD2:SPICD0) configure the rate of the SPI Baud Rate Generator after clock
source is selected and pre-scaled. Table 16.9 shows various SPCLK frequencies. The columns for PLL
Source show the frequencies when the PLL source is pre-scaled and divided down. The ROSC column
shows the relationship between the ring oscillator frequency and the divider bits. Note when the ring
oscillator is selected, the SPCLK frequency will vary since the ring oscillator (ROSC) frequency varies
from 4MHz to 12MHz
.
Table 16.9 SPCLK Frequencies
PLL SOURCE
DIVIDE
SPICD2 BIT SPICD1 BIT SPICD0 BIT
RATIO
4 MHZ
8 MHZ
12 MHZ
ROSC
0
0
1
0
1
0
1
0
1
0
1
0
1
1
2
4 MHz
2 MHz
8 MHz
4 MHz
12 MHz
6 MHz
ROSC / 1
ROSC / 2
ROSC / 4
ROSC / 8
ROSC / 16
ROSC / 32
ROSC / 64
4
1 MHz
2 MHz
3 MHz
8
500 kHz
250 kHz
125 kHz
62.5 kHz
31.3 kHz
1 MHz
1.5 MHz
750 kHz
375 kHz
187.5 kHz
1
16
32
64
128
500 kHz
250 kHz
125 kHz
62.5 kHz
93.75 kHz ROSC / 128
Revision 1.1 (01-14-03)
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