Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit command data to the slave. This particular
slave device drives '0' on the SPDIN pin to the master while it is accepting command data. This
SPIDR data is ignored.
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Next, a dummy 8 bit data value (any value) as written to the SPIDR. The SPI master automatically
clears the nBUSY bit, begins shifting the dummy data value onto the SPDOUT pin, and drives the
SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted. The data now contained in SPIDR is the first half of a valid 16 bit ADC value. SPIDR is
read and stored.
The final SPI cycle is initiated when another 8 bit data value is written to the SPIDR. Note that this
value may be another dummy value or it can be a new 8 bit command to be sent to the ADC. The
new command will be transmitted while the final data from the last command is received
simultaneously. This overlap allows ADC data to be read every 16 SPCLK cycles after the initial 24
clock cycle. The SPI master automatically clears the nBUSY bit, begins shifting the data value onto
the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled on each clock.
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After 8 clocks, the final SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt
is asserted. The data now contained in SPIDR is the second half of a valid 16 bit ADC value. SPIDR
is read and stored.
If a command was overlapped with the received data in the final cycle, #CS should remain asserted
and the SPI master will initiate another SPI cycle. If no new command was sent, #CS is released
and the SPI is idle.
16.10.1.2 Read/Write
The slave device used in this example is a Fairchild NS25C640 FM25C640 64K Bit Serial EEPROM.
The following sub-sections describe the read and write sequences.
Read
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The MISC10 bit is '1' and SPIMODE bit is deasserted '0' to enable the SPI interface in Full Duplex
mode.
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The CLKPOL, TCLKPH and RCLKPH bits are deasserted '0' to match the clocking requirements of
the slave device.
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The LSBF bit is deasserted '0' to indicate that the slave expects data in MSB-first order.
Assert CS# low using a GPIO pin.
Write a valid command word (as specified by the slave device) to the SPI Data register (SPIDR)
with nBUSY deasserted '1'. The SPI master automatically clears the nBUSY bit, begins shifting the
data value onto the SPDOUT pin, and drives the SPCLK pin. Data on the SPDIN pin is also sampled
on each clock.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit command data to the slave. This particular
slave device tri-states the SPDIN pin to the master while it is accepting command data. This SPIDR
data is ignored.
USER’S NOTE: External pull-up or pull-down is required on the SPDIN pin if it is tri-stated by the slave device.
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Next, EEPROM address A15-A8 is written to the SPIDR. The SPI master automatically clears the
nBUSY bit, begins shifting the address value onto the SPDOUT pin, and drives the SPCLK pin. Data
on the SPDIN pin is also sampled on each clock. Note: The particular slave device ignores address
A15-A13.
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After 8 clocks, the SPI cycle is complete, nBUSY is deasserted '1', and the SPIDONE interrupt is
asserted (See Section 16.8, "SPIDONE - 8051 Interrupt"). The data now contained in SPIDR is
invalid since the last cycle was initiated solely to transmit address to the slave. This particular slave
Revision 1.1 (01-14-03)
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SMSC LPC47N350
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