Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
16.7.3 SPIDR - SPI Data Register
Table 16.6 SPI Data Register (SPIDR)
N/A
HOST
ADDRESS
BDh
8051 ADDRESS
POWER
VCC1
00h on VCC1 POR
and when MISC10 bit
changes
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
R/W
See
R/W
See
R/W
See
R/W
See
R/W
See
R/W
See
R/W
See
R/W
See
8051 R/W
BIT NAME
Note 16.1 Note 16.1 Note 16.1 Note 16.1 Note 16.1 Note 16.1 Note 16.1 Note 16.1
SPIDR7
SPIDR6
SPIDR5
SPIDR4
SPIDR3
SPIDR2
SPIDR1
SPIDR0
A write to this register with the nBUSY bit deasserted '1' initiates an SPI transaction. At the end of an
SPI transaction, SPIDR contains serial input data (valid or not) from the last transaction. Writes to
SPIDR with the nBUSY bit asserted '0' are ignored.
Note 16.1 There are two SPI Data Registers that share the same address - one read only and one
write only. However, reading the data register immediately after the data register is written
may return invalid data. Reading the data register in the middle of SPI transaction will return
invalid data. Any writes to the data register in the middle of SPI transaction is ignored.
Revision 1.1 (01-14-03)
182
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
