Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 16.3 LPC47N350 - SPI Registers
DESCRIPTION
REGISTER
SPICR
SPISR
SPIDR
SPICC
SPIBR
SPI Control Register
SPI Status Register
SPI Data Register
SPI Clock Control Register
SPI Baud Rate Register
16.7.1 SPICR - SPI Control Register
Table 16.4 SPI Control Register (SPICR)
N/A
HOST ADDRESS
8051 ADDRESS
POWER
BBh
VCC1
00h on VCC1 POR
and when MISC10 bit
changes
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R/W
R/W
R/W
Reserved
BIOEN
SPIMODE LSBF
16.7.1.1 D0 - LSBF - Least Significant Bit First
When LSBF is deasserted '0', the 8-bit value from the SPI data register is transferred across the SPI
interface in MSB-first order. When LSBF is asserted '1', the data is transferred in LSB-first order.
16.7.1.2 D1 - SPIMODE - SPI Mode
This bit configures the interface for Bidirectional or Full Duplex mode. When SPIMODE is deasserted
'0', the interface will operate in Full Duplex mode (See Section 16.5.1, "Full Duplex Mode"). When
SPIMODE is asserted '1', the interface will operate in Bidirectional mode (See Section 16.5.2,
"Bidirectional Mode").
16.7.1.3 D2 - BIOEN - Bidirectional Mode Output Enable
When the SPI is configured for Bidirectional Mode (see Section 16.7.1.2, "D1 - SPIMODE - SPI Mode"),
the BIOEN bit controls access to SDOUT. When BIOEN is deasserted '0', the SDOUT signal is
configured as the serial data input. When BIOEN is asserted '1', the SDOUT signal is configured as the
serial data output. See Figure 16.1 for details.
Revision 1.1 (01-14-03)
180
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
