Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
■
Every data exchange is a simultaneous transmit and receive operation. Data shifted out of the
master is shifted into the slave and data shifted out of the slave is shifted into the master
synchronized by the master-driven SPCLK.
16.5.2 Bidirectional Mode
■
■
■
SPI data can be transmitted and received over a single data line using Bidirectional mode. See
Section 16.7.1.2, "D1 - SPIMODE - SPI Mode," on page 180 for SPI mode configuration.
Input and output serial data share the SDOUT pin, as shown in Figure 16.1 on page 175 using the
BIOEN bit (See Section 16.7.1.3, "D2 - BIOEN - Bidirectional Mode Output Enable," on page 180).
The Software driver must properly drive the BIOEN bit and store received data depending on the
transaction format of the specific slave device.
16.5.3 Baud Rate Generator
■
The SPI Baud Rate Generator divides the SPI input clock to provide a SPCLK for SPI peripheral of
various frequencies.
■
The LPC47N350 SPI can be configured to run from the Ring Oscillator or a PLL source (See Section
16.7.4.3, "D2 - CLKSRC - SPI Clock Source," on page 183 and Section 16.7.4.4, "D3 - CLKEN -
Clock Enable," on page 183). The PLL uses the 14.318 MHz input clock and is active under VCC2
power only. The Ring Oscillator frequency range is from 4MHz to 12 MHz. See Figure 16.1.
USER’S NOTE: The CLKSRC bit shouldn't be changed during SPI transaction.
■
If the PLL output is selected, the SPICS0 and SPICS1 bits (See Section 16.7.5.2, "D7:D6 - PLL
Clock Scale Bits," on page 185) in the SPI Baud Rate register can be used to scale the input clock
(4 MHz, 8 MHz or 12 MHz) to the SPI Baud Rate Generator. If the ring oscillator is selected the
SPICS0 and SPICS1 bits are ignored and the ring oscillator clock output is directly connected to the
SPI Baud Rate Generator (see Section 16.7.5.1, "D2:D0 - SPI Clock Divider Bits," on page 184).
■
The divisor bits (SPICD0, SPICD1 and SPICD2 - (see Section 16.7.5.1, "D2:D0 - SPI Clock Divider
Bits," on page 184) in the SPI Baud Rate register can be programmed to divide down the clock from
1 to 128. Note that ring oscillator output varies from 4 MHz to 12 MHz. The actual SPCLK
frequency will vary. The actual frequency of the ring oscillator can be determined by a proper
algorithm. Describing such algorithm is beyond the scope of this document.
■
■
The PLL will be stopped when VCC2 is removed. The input clock to the SPI block can be switched
to ring oscillator, using the CLKSRC bit to operate the SPI Block, when VCC2 is removed.
The 8051 should not be put into sleep mode in the middle of a transaction. If the 8051 goes in the
sleep mode in the middle of a SPI transaction, the SPI transaction will be suspended. All the clocks
to 8051, including PLL and ring oscillator, are stopped when 8051 is in the sleep mode.
16.6
External Interrupt from SPI Slave Device to Wake Up 8051
USER’S NOTE: External SPI slave devices that need to wakeup 8051 (when 8051 is in the sleep mode) can do so
using a GPIO that is part of 8051 wakeup sources. An example is a Temperature Sensor slave
device that compares the temperature reading with a set limit. If the temperature reading goes
beyond the set limit, the slave device generates an interrupt to wakeup 8051 which processes the
interrupt accordingly.
16.7
SPI Registers
There are 5 registers with which to control and monitor the status of the LPC47N350 SPI. These
registers are 8051 MMCRs (See Table 7.7 on page 50). These registers return to their default values
when the SPI is switched (using the MISC10 bit) from GPIO to SPI mode and from SPI to GPIO mode
(See Section 16.4, "SGPIO vs. SPI Function Control") AND on VCC1 POR.
SMSC LPC47N350
179
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
