Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
16.5
Functional Description
During a typical SPI transfer, data is shifted out of the SPI master and received by an SPI slave. Data
is also shifted out of the slave and received by the master. The duration of the data transfer cycle
depends on the mode chosen - Bidirectional or Full Duplex. Data is shifted and latched by both the
master and slave using an I/O shift register in each device. These registers are clocked by a serial clock
which is generated by the master only during a transfer. Figure 16.2 illustrates SPI transfer logic.
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SPDOUT
SPDIN
SPCLK
SPI MASTER
SPI SLAVE
Figure 16.2 SPI Logic (Full Duplex)
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The LPC47N350 SPI Interface contains an 8-bit shift register and therefore must transmit and
receive data in 8-bit cycles. Communication with SPI peripherals that have input registers of varying
lengths can be achieved with multiple 8-bit cycles and/or leading zeros in the command stream.
The LPC47N350 SPI can be configured to operate in two modes: Full Duplex and Bidirectional (see
Figure 16.1 on page 175). See Section 16.5.1, "Full Duplex Mode" and Section 16.5.2, "Bidirectional
Mode" for detailed descriptions of each operating mode.
All SPI transactions (send or receive) are initiated by writing a value to the SPI Data register (Section
16.7.3, "SPIDR - SPI Data Register") with the nBUSY bit deasserted '1' (Section 16.7.2.1, "D0 -
nBUSY (Status)"). If only receive data is desired, a dummy data value must be written to SPIDR to
start the packet transfer. If only transmit data is to be sent, invalid data will also be sampled from
SPDIN and will be loaded into SPIDR at the end of the transaction.
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All received data can be sampled on a rising or falling SPCLK edge using RCLKPH (See Section
16.7.4.5, "D4 - RCLKPH - Receive Clock Phase" for clock controls). This clock setting must be
identical to the clocking requirements of the current SPI slave.
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The transmit data is shifted out on the edge as selected by TCLKPH bit in the SPICC register (see
Section 16.7.4.1, "D0 - TCLKPH - Transmit Clock Phase").
The nBUSY bit (SPISR - Section 16.7.2.1, "D0 - nBUSY (Status)") is asserted '0' when a transfer is
in progress and is deasserted '1' when a transfer is complete. A completed transfer also asserts the
SPIDONE interrupt (See Section 16.8, "SPIDONE - 8051 Interrupt").
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When a transaction is completed in the full-duplex mode, the SPIDR always contains received data
(valid or not) from the last transaction. When transmission is completed in the bi-directional mode,
the SPIDR contains the transmitted data. When receive transaction is completed in the bi-directional
mode, the SPIDR contains the received data. The length and order of data sent to and received
from a SPI peripheral varies between peripheral devices. The SPI must be properly configured and
software-controlled to communicate with each device and determine whether SPIDR data is valid
slave data.
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Common peripheral devices require a chip select signal to be asserted during a transaction. Chip
selects for SPI devices may be controlled by LPC47N350 GPIO pins.
16.5.1 Full Duplex Mode
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In Full Duplex Mode, serial data is transmitted and received simultaneously by the SPI master over
two separate data transmission lines as shown in Figure 16.1 on page 175. See Section 16.7.1.2,
"D1 - SPIMODE - SPI Mode," on page 180 for SPI mode configuration.
Revision 1.1 (01-14-03)
178
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
