Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 15.5 Own Address Register
N/A
HOST ADDRESS
8051 ADDRESS
2
I C/SMBus 1
= 0x7F32
2
I C/SMBus 2
= 0x7F68
VCC1
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Reserved
Slave
Slave
Slave
Slave
Address
3
Slave
Address
2
Slave
Slave
BIT NAME
Address Address Address
Address Address
6
5
4
1
0
15.2.4 Data Register
2
The Data Register acts as serial shift register and read buffer interfacing to the I C/SMBus. All read
2
2
and write operations to/from the I C/SMBus are done via this register. I C/SMBus data is always shifted
in or out of the Data Register.
2
In receiver mode, the I C/SMBus data is shifted into the shift register until the acknowledge phase.
Further reception of data is inhibited (SCL held low) until the Data Register is read.
2
In the transmitter mode, data is transmitted to the I C/SMBus as soon as it is written to the Data Register
if the serial I/O is enabled (ESO=1).
SMSC LPC47N350
171
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
