Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
2
15.2.2 I C/SMBus Status Register
2
Table 15.4 I C/SMBus Status Register
N/A
HOST ADDRESS
8051 ADDRESS
2
I C/SMBus 1
= 0x7F31
2
I C/SMBus 2
= 0x7F67
VCC1
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
R
R
R
R
R
R
R
R
PIN
Reserved STS
BER
LRB/AD0 AAS
LAB
nBB
BIT 7 - PIN
Pending Interrupt Not. This bit is a status flag which is used to synchronize serial communication and
is set to logic “0” whenever the chip requires servicing. The PIN bit is normally read in polled
2
applications to determine when an I C/SMBus byte transmission/reception is completed.
When acting as transmitter, PIN is set to logic “1” (inactive) each time the Data Register is written. In
receiver mode, the PIN bit is automatically set to logic “1” each time the Data Register is read.
2
After transmission or reception of one byte on the I C/SMBus (nine clock pulses, including
acknowledge), the PIN bit will be automatically reset to logic “0” (active) indicating a complete byte
transmission/reception. When the PIN bit is subsequently set to logic “1” (inactive), all status bits will
be reset to “0” on a BER (bus error) condition.
In polled applications, the PIN bit is tested to determine when a serial transmission/reception has been
completed. When the ENI bit (bit 3 of the Control Register) is also set to logic “1,” the hardware interrupt
is enabled. In this case, the PI flag also triggers and internal interrupt (active low) via the nINT output
each time PIN is reset to logic “0”.
2
When acting as a slave transmitter or slave receiver, while PIN = “0”, the chip will suspend I C/SMBus
transmission by holding the SCL line low until the PIN bit is set to logic “1” (inactive). This prevents
further data from being transmitted or received until the current data byte in the Data Register has been
read (when acting as slave receiver) or the next data byte is written to the Data Register (when acting
as slave transmitter).
PIN Bit Summary:
■
The PIN bit can be used in polled applications to test when a serial transmission has been
completed. When the ENI bit is also set, the PIN flag sets the internal interrupt via the nINT output.
2
■
In transmitter mode, after successful transmission of one byte on the I C/SMBus, the PIN bit will be
automatically reset to logic “0” (active) indicating a complete byte transmission.
■
■
In transmitter mode, PIN is set to logic “1” (inactive) each time the Data Register is written.
In receiver mode, PIN is set to logic “0” (inactive) on completion of each received byte.
Subsequently, the SCL line will be held low until PIN is set to logic “1”.
SMSC LPC47N350
169
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
