Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
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In receiver mode, when the Data Register is read, PIN is set to logic “1” (inactive).
2
In slave receiver mode, an I C/SMBus STOP condition will set PIN=0 (active).
PIN=0 if a bus error (BER) occurs.
BIT 6 - Reserved (Read returns 0)
BIT 5 - STS
When in slave receiver mode, this flag is asserted when an externally generated STOP condition is
detected (used only in slave receiver mode).
BIT 4 - BER
Bus error; a misplaced START or STOP condition has been detected. Resets nBB (to logic “1”;
inactive), sets PIN = “0” (active).
BIT 3 - LRB/AD0
Last Received Bit or Address 0 (general call) bit. This status bit serves a dual function, and is valid
only while PIN=0.
2
LRB holds the value of the last received bit over the I C/SMBus while AAS=0 (not addressed as slave).
Normally, this will be the value of the slave acknowledgment; thus checking for slave acknowledgment
is done via testing of the LRB.
2
When AAS = 1 (Addressed as slave condition), the I C/SMBus controller has been addressed as a
slave. Under this condition, this bit becomes the AD0 bit and will be set to logic “1” if the slave address
2
received was the ‘general call’ (00h) address, or logic “0” if it was the I C/SMBus controller’s own slave
address.
BIT 2 - AAS
Addressed As Slave bit. Valid only when PIN=0. When acting as slave receiver, this flag is set when
2
an incoming address over the I C/SMBus matches the value in own address register S0’ (shifted by one
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bit) or if the I C/SMBus ‘general call’ address (00h) has been received (‘general call’ is indicated when
AD0 status bit is also set to logic “1”).
BIT 1 - LAB
Lost Arbitration Bit. This bit is set when, in multi-master operation, arbitration is lost to another master
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on the I C/SMBus.
BIT 0 - nBB
2
Bus Busy bit. This is a read-only flag indicating when the I C/SMBus is in use. A zero indicates that
the bus is busy, and access is not possible. This bit is set/reset (logic “1”/logic “0”) by Stop/Start
conditions.
15.2.3 Own Address Register
2
When the chip is addressed as slave, this register must be loaded with the 7-bit I C/SMBus address to
which the chip is to respond. During initialization, the Own Address Register must be written to,
regardless whether it is later used. The Addressed As Slave (AAS) bit in the Status Register is set
when this address is received (the value in the Data Register is compared with the value in the Own
Address Register). Note that the Data Register and Own Address Register are offset by one bit; hence,
programming the Own Address Register with a value of 55h will result in the value AAh being recognized
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as the chip’s I C/SMBus slave address.
After reset, the Own Address Register has default address 00h.
Revision 1.1 (01-14-03)
170
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
