Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Chapter 16 Serial Peripheral Interface (SPI)
16.1
Overview
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The LPC47N350 SPI port is a configurable 3-wire serial interface for communicating with various
peripheral devices (EEPROMS, DACs, ADCs).
8-bit serial data is transmitted and received simultaneously over two data pins in Full Duplex mode
with options to transmit and receive on one data pin in Bidirectional mode.
An internal programmable Baud Rate Generator and clock polarity and phase controls allow
communication with various SPI peripherals with specific clocking requirements.
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SPI cycle completion can be determined by status polling or interrupts.
The SPI port pins can be configured as GPIOs when SPI functionality is not needed.
The LPC47N350 SPI is a master only device and does not support multiple-master SPI
configurations.
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The SPI is powered by VCC1 and can run on suspend power only.
16.2
SPI Block Diagram
Figure 16.1 shows the SPI block diagram. See Section 16.3, "Interface Description," on page 176,
Section 16.4, "SGPIO vs. SPI Function Control," on page 177, Section 16.7, "SPI Registers," on
page 179, and Section 16.8, "SPIDONE - 8051 Interrupt," on page 185 for description on SPI block
signals, SPI pins and registers.
SPI Block
VCC1
Powerdown/Disable SPI Block
or
PWRDWN
RESET
MISC10
VCC1 POR
Reset to Counters, Registers and
other internal logic
SPINT
REG_BC_SEL
REG_BB_SEL
nBUSY
SPIDONE
SPISR Reg
LSBF, SPIMODE,
BIOEN
SPICR Reg
SPICC Reg
SPIBR Reg
CLKPOL, CLKSRC, CLKEN,
TCLKPH, RCLKPH
REG_BE_SEL
REG_BF_SEL
To GPIO vs.
SPDIN Function
Control
SPICD[2:0],
SPIMODE
SPICS[1:0]
CLK
SPDIN1
PAD
PAD
0
1
SPDIN
LSBF
SPDIN2
SPDO
REG_BD_SEL
SPI_DI [7:0]
SPI_DO [7:0]
nRD
SPIDR Register
BIOEN
SPDOUT
BIOEN
SPICS0 SPICS1
nWRT
CLK CLKPOL
CLKPH
14.318
MHz
Pre-Scaler
EN
48MHz_IN
PLL
1
0
SPCLKO
Polarity
PAD
SPCLK
Divider
ROSC
Ring Oscillator
(4 MHz to 12 MHz)
SPICD [2:0]
CLKEN
CLKSRC
Note: Although not shown, the SPI
functions are muxed with GPIO functions
on the pins.
Note: The SPI Block diagram is not shown in complete
details. It may not represent the actual implementation.
Figure 16.1 SPI Block Diagram
SMSC LPC47N350
175
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
