Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
2
2
I C/SMBus Reset. Setting this bit re-initializes all logic and registers in the I C/SMBus block. AB_RST
is not self-clearing. It must be written high and then written low.
BITS 6 through 3 – Reserved (Reads return 0)
BIT 2 - CLK_DIV
2
Clock Divider Bit. The clock divider bit CLK_DIV affects all I C/SMBus clock inputs. When CLK_DIV is
2
2
“1”, the I C/SMBus input clock is divided by 2. When CLK_DIV is “0”, the I C/SMBus input clock is not
divided.
BITS 1 and 0 – CLOCK SELECT
2
Clock Selection Bits. These bits determine the source of the clock used by the I C/SMBus Controller.
Encoding of these bits are as shown in Table 15.7, "Clock Register", above. Data rates produced by the
selected clock are shown in Table 15.8.
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Table 15.8 Internal Clock Rates and I C/SMBus Data Rates
NOMINAL
HIGH
NOMINAL
LOW
MINIMUM
HIGH
DATA RATE
(F/240)
CLOCK SELECT
CLOCK RATE
(96/F)
(144/F)
(18/F) Note 15.7
00
01
Off
n/a
-
-
-
-
-
-
-
-
10
Ring Osc=4 MHz
Ring Osc=6 MHz
Ring Osc=8 MHz
12 MHz
16.7 KHz
25 KHz
33.3 KHz
50 KHz
67 KHz
100 KHz
133 KHz
100 KHz
24 µs
16 µs
12 µs
8 µs
6 µs
4 µs
3 µs
4 µs
36 µs
24 µs
18 µs
12 µs
9 µs
6 µs
4.5 µs
6 µs
4.5 µs
3 µs
2.25 µs
4 µs
4 µs
4 µs
4 µs
4 µs
(8051 Clock
Selection)
16 MHz
24 MHz
32 MHz
11
24 MHz
f = frequency of the ring oscillator.
Note 15.7 18/f pertains to Ring Osc rates only.
2
15.2.6 I C/SMBus Switch Register
2
2
2
The I C/SMBus Switch register is used to control the I C/SMBus Multiplexer. Each of the two I C/SMBus
controllers in the LPC47N350 can drive two independent sets of Clock and Data pins (Figure 15.1). The
2
2
selected Clock and Data pins for each I C/SMBus controller are determined by the I C_SMBusA_SEL_A
and I2C_SMBusB_SEL_A bits, D1 and D0 respectively, in the I C/SMBus Switch register.
2
SMSC LPC47N350
173
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
