Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
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These bits control the generation of the I C/SMBus Start condition and transmission of slave address
and R/nW bit, generation of repeated Start condition, and generation of the STOP condition (see
Table 15.3).
Table 15.3 Instruction Table for Serial Bus Control
PRESENT
STA
STO
MODE
FUNCTION
START
OPERATION
1
0
SLV/REC
Transmit START+address,
remain MST/TRM if R/nW=0;
go to MST/REC if R/nW=1.
1
0
0
1
MST/TRM
REPEAT START
Same as for SLV/REC
MST/REC;
MST/TRM
STOP READ;
STOP WRITE
Transmit STOP go to SLV/REC mode; Note 15.4
1
0
1
0
MST
DATA CHAINING
Send STOP, START and address after last master
frame without STOP sent; Note 15.5
ANY
NOP
No operation; Note 15.6
Note 15.4 In master receiver mode, the last byte must be terminated with ACK bit high (‘negative
acknowledge’).
Note 15.5 If both STA and STO are set high simultaneously in master mode, a STOP condition
followed by a START condition + address will be generated. This allows ‘chaining’ of
transmissions without relinquishing bus control.
Note 15.6 All other STA and STO mode combinations not mentioned in Table 15.1 are NOPs.
BIT 0 - ACK
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This bit must be set normally to logic “1”. This causes the I C/SMBus to send an acknowledge
automatically after each byte (this occurs during the 9th clock pulse). The bit must be reset (to logic “0”)
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when the I C/SMBus controller is operating in master/receiver mode and requires no further data to be
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sent from the slave transmitter. This causes a negative acknowledge on the I C/SMBus, which halts
further transmission from the slave device.
Revision 1.1 (01-14-03)
168
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
