Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
2
Table 15.9 I C/SMBus Switch Register
N/A
HOST ADDRESS
8051 ADDRESS
POWER
0x7F89
VCC1
0x03
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R
R
R
R
R
R
R/W
R/W
Reserved
I2C_SMBusB I2C_SMBusA
BIT NAME
_SEL_A
_SEL_A
Note: BITS 7 through 2 – Reserved (Reads return 0)
BIT 1 - I2C_SMBusB_SEL_A
2
The I2C_SMBusB_SEL_A bit determines the selected Clock and Data pins for the I C/SMBus 2
controller (Figure 15.1). When the I2C_SMBusB_SEL_A bit is ‘1’ (default), the AB2A_CLOCK and
2
AB2A_DATA pins are driven by the I C/SMBus B controller. The AB2B_CLOCK and AB2B_DATA pins
are tristated. When the I2C/SMBusB_SEL_A bit is ‘0’, the AB2B_CLOCK and AB2B_DATA pins are
2
driven by the I C/SMBus 2 controller. The AB2A_CLOCK and AB2A_DATA pins are tristated.
BIT 0 - I2C_SMBusA_SEL_A
2
The I2C_SMBusA_SEL_A bit determines the selected Clock and Data pins for the I C/SMBus 1
controller (Figure 15.1). When the I2C_SMBusA_SEL_A bit is ‘1’ (default), the AB1A_CLOCK and
2
AB1A_DATA pins are driven by the I C/SMBus 1 controller. The AB1B_CLOCK and AB1B_DATA pins
are tristated. When the I2C_SMBusA_SEL_A bit is ‘0’, the AB1B_CLOCK and AB1B_DATA pins are
2
driven by the I C/SMBus 1 controller. The AB1A_CLOCK and AB1A_DATA pins are tristated.
Revision 1.1 (01-14-03)
174
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
