Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
Table 15.6 Data Register
N/A
HOST ADDRESS
8051 ADDRESS
2
I C/SMBus 1
= 0x7F33
2
I C/SMBus 2
= 0x7F69
VCC1
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Data Bit 7
Data Data Bit 5 Data Bit 4 Data Bit 3 Data Bit 2 Data Bit 1 Data Bit 0
Bit 6
BIT NAME
15.2.5 Clock Register
2
The Clock Register controls selection of the internal chip clock frequency used for the I C/SMBus block.
This determines the SCL clock frequency generated by the chip. The selection is made via Bits[2:0].
Table 15.7 Clock Register
N/A
HOST ADDRESS
8051 ADDRESS
2
I C/SMBus 1
= 0x7F34
2
I C/SMBus 2
= 0x7F6A
VCC1
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
R/W
R
R
R
R
R/W
R/W
R/W
AB_RST
Reserved
CLK_DIV CLOCK SELECT
00 = Clock Off
BIT NAME
01 = Reserved
10 = 8051 Clock
11 = 24 MHz. Clock
BIT 7 – AB_RST
Revision 1.1 (01-14-03)
172
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
