Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
15.2
I2C/SMBus Register Descriptions
2
Each I C/SMBus controller has five internal registers. Two of these, Own Address Register and Clock
Register, are used for initialization of the controller. Normally they are only written once directly after
resetting of the chip. The other registers, Data Register, Control Register and Status Register are used
during actual data transmission/reception. The Control Register and Status Register are accessed at the
2
same location. The Data Register performs all serial-to-parallel interfacing with the I C/SMBus interface.
2
The Status Register contains I C/SMBus status information required for bus access and/or monitoring.
2
The I C/SMBus Switch Register is used to select one of two sets of Clock and Data pins for each
controller.
2
15.2.1 I C/SMBus Control Register
2
Table 15.2 I C/SMBus Control Register
N/A
HOST ADDRESS
8051 ADDRESS
2
I C/SMBus 1
= 0x7F31
2
I C/SMBus 2
= 0x7F67
VCC1
POWER
0x00
DEFAULT
BIT
D7
D6
D5
D4
D3
D2
D1
D0
-
-
-
-
-
-
-
-
HOST TYPE
8051 R/W
BIT NAME
W
W
W
W
W
W
W
W
PIN
ESO Reserved
ENI
STA
STO
ACK
BIT 7 - PIN
Pending Interrupt Not. Writing the PIN bit to a logic “1” deasserts all status bits except for the nBB (Bus
Busy); nBB is not affected. The PIN bit is a self-clearing bit. Writing this bit to a logic “0” has no effect.
This may serve as a software reset function.
BIT 6 - ESO
2
Enable Serial Output. ESO enables or disables the serial I C/SMBus I/O. When ESO is high,
2
I C/SMBus communication is enabled; communication with the Data Register is enabled and the Status
Register bits are made available for reading. With ESO = 0, bits ENI, STA, STO and ACK of the Control
Register can be read for test purposes.
BIT 5 and 4 - Reserved
BIT 3 - ENI
This bit enables the internal interrupt, nINT, which is generated when the PIN bit is active (logic 0).
BIT 2 and 1 - STA and STO
SMSC LPC47N350
167
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
