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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Chapter 15 I2C/SMBus  
15.1  
Overview  
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The LPC47N350 supports I C/SMBus. I C/SMBus is a serial communication protocol between a  
computer host and its peripheral devices. It provides a simple, uniform and inexpensive way to connect  
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peripheral devices to a single computer port. A single I C/SMBus controller on a host can accommodate  
up to 125 peripheral devices.  
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The I C/SMBus protocol includes a physical layer and several software layers. The software layers  
include the base protocol, the device driver interface, and several specific device protocols.  
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The LPC47N350 implements two I C/SMBus controllers (I C/SMBus 1 Controller and I C/SMBus 2  
Controller). Each controller, through a multiplexer, can drive two independent sets of Clock and Data  
pins, as shown in Figure 15.1, "I2C/SMBus Controllers".  
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Four I C/SMBus 2 controller pins, AB2A_DATA, AB2A_CLK, AB2B_DATA and AB2B_CLK are  
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multiplexed on GPIO11 through GPIO14. For information regarding multiplexed I C/SMBus pins see  
Table 2.4 on page 10 and Section 21.5, "Multiplexing_3 Register - MISC[23:17]".  
APPLICATION NOTE: When VCC1=0, the I2C bus pins present a high impedance and draw only leakage current.  
Therefore no additional external circuity is required to isolate the LPC47N350 Vcc1 powered  
the I2C bus pins from an I2C bus with VCC0 powered devices and/or resistor pull-ups to  
VCC0.  
2
The I C/SMBus interface is fully and directly controlled by the on-chip 8051 through its set of on-chip  
memory mapped control registers. Addresses for the registers are shown in Table 15.1, "I2C/SMBus  
Register Address Summary".  
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The I C/SMBus logic is powered on the VCC1 power plane and clocked by the 8051 clock to provide  
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the ability to wake-up the 8051 on an I C/SMBus event. When a wakeup event occurs, there is a 6 µs  
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max. delay before the ring oscillator starts and an I C/SMBus event can be detected. This limits the  
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I C/SMBus Bus Master Operating Frequency for wakeup events to 60 KHz. Once the ring oscillator is  
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running, the I C/SMBus Operating Frequency is a full 100 KHz.  
SMSC LPC47N350  
165  
Revision 1.1 (01-14-03)  
DATASHEET