Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
13.4
GATEA20 Hardware Speed-Up
GATEA20 is multiplexed onto GPIO17 using MISC6. The LPC47N350 contains on-chip logic support
for the GATEA20 hardware speed-up feature. GATEA20 is part of the control required to mask address
line A20 to emulate 8086 addressing.
In addition to the ability for the host to control the GATEA20 output signal directly, a configuration bit
called "SAEN" (Software Assist Enable, bit 1 of Configuration register 0) is provided; when set, SAEN
allows firmware to control the GATEA20 output.
When SAEN is set, a 1-bit register assigned to address 7FFBH controls the GATEA20 output. The
register bit allocation is shown in Table 13.12.
Table 13.12 Register Bit Allocation
D7
x
D6
x
D5
x
D4
x
D3
x
D2
x
D1
x
D0
GATEA20
Writing a "0" into location D0 causes the GATEA20 output to go low, and vice versa. When the register
at location 7FFBH is read, all unused bits (D7-D1) are read back as "0".
Host control and firmware control of GATEA20 affect two separate register elements. Read back of
GATEA20 through the use of 7FFBH reflects the present state of the GATEA20 output signal: if SAEN
is set, the value read back corresponds to the last firmware-initiated control of GATEA20; if SAEN is
reset, the value read back corresponds to the last host-initiated control of GATEA20.
Host control of the GATEA20 output is provided by the hardware interpretation of the "GATEA20
sequence" (see Table 13.13). The foregoing description assumes that the SAEN configuration bit is
reset.
When the LPC47N350 receives a "D1" command followed by data (via the host interface), the on-chip
hardware copies the value of data bit 1 in the received data field to the GATEA20 host latch. At no time
during this host-interface transaction will PCOBF or the IBF flag (bit 1) in the Status register be activated;
i.e., this host control of GATEA20 is transparent to firmware, with no consequent degradation of overall
system performance. Table 13.13 details the possible GATEA20 sequences and the LPC47N350
responses.
On VCC1 POR, GATEA20 will be set.
An additional level of control flexibility is offered via a memory-mapped synchronous set and reset
capability. Any data written to 7FFEH causes the GATEA20 host latch to be set; any data written to
7FFFH causes it to be reset. This control mechanism should be used with caution. It was added to
augment the "normal" control flow as described above, not to replace it. Since the host and the firmware
have asynchronous control capability of the host latch via this mechanism, a potential conflict could
arise. Therefore, after using the 7FFEH and 7FFFH addresses, firmware should read back the
GATEA20 status via 7FFBH (with SAEN = 0) to confirm the actual GATEA20 response.
Table 13.13 GATEA20 Command/Data Sequence Examples
SA2
R/W
D[0:7]
IBF FLAG
GATEA20
COMMENTS
1
0
1
W
W
W
D1
DF
FF
0
0
0
Q
1
GATEA20 Turn-on Sequence
1
1
0
1
W
W
W
D1
DD
FF
0
0
0
Q
0
GATEA20 Turn-off Sequence
0
SMSC LPC47N350
147
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
