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47N350 参数 Datasheet PDF下载

47N350图片预览
型号: 47N350
PDF下载: 下载PDF文件 查看货源
内容描述: LEGACY免费的键盘嵌入式控制器, SPI和LPC接口对接 [LEGACY FREE KEYBOARD EMBEDDED CONTROLLER WITH SPI AND LPC DOCKING INTERFACE]
分类和应用: 控制器PC
文件页数/大小: 346 页 / 4406 K
品牌: SMSC [ SMSC CORPORATION ]
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Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface  
Chapter 13 Keyboard Controller  
13.1  
8042 Style Host Interface  
The LPC47N350 keyboard controller uses a High-Performance 8051 microcontroller CPU core to  
produce a superset of the features provided by the industry-standard 8042 keyboard controller. Added  
features include two high-drive serial interfaces, and additional interrupt sources. The LPC47N350  
provides an industry standard 8042-style LPC host interface to the High-Performance 8051 to emulate  
standard 8042 keyboard controller and preserve software backward compatibility with the system BIOS.  
The LPC47N350’s LPC keyboard interface is functionally compatible with the 8042-style host interface.  
The keyboard controller has the KBD (Keyboard) Status register, KBD Data/Command Write register,  
and KBD Data Read register.  
Table 13.1 shows how the has the LPC interface accesses the keyboard controller. In addition to the  
above signals, the host interface includes keyboard and mouse interrupts.  
13.2  
Keyboard Controller Register Description  
Table 13.1 Keyboard Controller LPC I/O Address Map  
HOST ADDRESS  
COMMAND  
FUNCTION  
Keyboard Data Write (C/D=0)  
0x60  
Write  
Read  
Write  
Read  
Keyboard Data Read  
0x64  
Keyboard Command Write (C/D=1)  
Keyboard Status Read  
Note: These registers consist of three separate 8 bit registers: KBD Status, KBD Data/Command  
Write and KBD Data Read.  
13.2.1 Keyboard Data Write  
This is an 8 bit write only register. When written, the C/D status bit of the status register is cleared to  
zero and the IBF bit is set.  
13.2.2 Keyboard Data Read  
This is an 8 bit read only register. When read, the PBOBF and/or AUXOBF interrupts are cleared and  
the OBF flag in the status register is cleared.  
13.2.3 Keyboard Command Write  
This is an 8 bit write only register. When written, the C/D status bit of the status register is set to one  
and the IBF bit is set.  
13.2.4 Keyboard Status Read  
This is an 8 bit read only register. Refer to the description of the Status Register (7FF2H) for more  
information.  
SMSC LPC47N350  
143  
Revision 1.1 (01-14-03)  
DATASHEET