Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
13.2.5 8051-to-Host Keyboard Communication
The 8051 can write to the KBD Data Read register via address 7FF1H and 7FFAH (Aux Host Data
Register), respectively. A write to either of these addresses automatically sets bit 0 (OBF) in the Status
register. A write to 7FF1H also sets PCOBF. A write to 7FFAH also sets AUXOBF1. See Table 13.2.
Table 13.2 Host-Interface Flags
8051 ADDRESS
FLAG
PCOBF (KIRQ) output signal goes high
7FF1H (R/W)
7FFAH (W)
AUXOBF1 (MIRQ) output signal goes high
Table 13.3 Host I/F Data Register
HOST
0x60
8051
0x7FF1
VCC1
N/A
POWER
DEFAULT
The Input Data register and Output Data register are each 8 bits wide. A write to this 8 bit register by
the 8051 will load the Keyboard Data Read Buffer, set the OBF flag, and set the PCOBF output if
enabled. A read of this register by the 8051 will read the data from the Keyboard Data or Command
Write Buffer and clear the IBF flag. Refer to the PCOBF and Status register descriptions for more
information.
Table 13.4 Host I/F Command Register
HOST
0x64 (W)
0x7FF1
VCC1
8051
POWER
DEFAULT
N/A
The host CPU sends commands to the keyboard controller by writing command bytes to this register.
Table 13.5 Host I/F Status Register
HOST
0x64 (R)
0x7FF2
VCC1
N/A
8051
POWER
DEFAULT
The Status register is 8 bits wide. Shows the contents of the KBD Status register.
Table 13.6 KBD Status Register
D7
D6
D5
D4
D3
D2
D1
D0
UD
UD
AUXOBF/UD
UD
C/D
UD
IBF
OBF
This register is read-only for the Host and read/write by the 8051. The 8051 cannot write to bits 0, 1,
or 3 of the Status register.
Revision 1.1 (01-14-03)
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SMSC LPC47N350
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