Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
The PCOBF register is also readable; bits 1-7 will return a "0" on the read back. The value read back
on bit 0 of the register always reflects the present value of the PCOBF output. If PCOBFEN = 1, then
this value reflects the output of the firmware latch at 7FFDH. If PCOBFEN = 0, then the value read back
reflects the in-process status of write cycles to 7FF1H (i.e., if the value read back is high, the host
interface output data register has just been written to). If OBFEN=0, then KIRQ is driven inactive (low).
13.3.2 AUXOBF1 Description
(The following description assumes that OBFEN = 1 in Configuration Register 0); This bit is multiplexed
onto MIRQ. The AUXOBF1/MIRQ signal is a system interrupt which signifies that the 8051 has written
to the output data register via address 7FFAH.
On power-up, after VCC1 POR, AUXOBF1 is reset to 0. AUXOBF1 will normally reflects the status of
writes to 7FFAH. (MIRQ is normally selected as IRQ12 for mouse support). AUXOBF1 is cleared by
hardware on a read of the Host Data Register. If OBFEN=0, then KIRQ is driven inactive (low).
Table 13.8 Status and Interrupt Behavior of Writing to Output Data Register
HOST I/F STATUS REGISTER BITS
Write to Register
7FF1
AUXOBF (D5)
OBF (D0)
OBFEN=0
KIRQ=0
OBFEN=1
KIRQ=1
0
1
1
1
7FFA
MIRQ=0
MIRQ=1
Table 13.9 OBFEN and PCOBFEN Effects on KIRQ
PCOBFEN
OBFEN
0
1
X
0
1
KIRQ is inactive and driven low
KIRQ = PCOBF@7FF1
KIRQ = PCOBF@7FFD
Table 13.10 OBFEN and AUX Effects on MIRQ
OBFEN
AUXH
0
1
X
0
1
MIRQ is inactive and driven low
MIRQ = PCOBF@7FFA; Status Register D5 = User Defined
MIRQ = PCOBF@7FFA; Status Register D5 = Hardware Controlled
13.3.2.1 8051 AUXOBF1 Control Register
Table 13.11 AUX Host Data Register
HOST
0x60
8051
0x7FFA
VCC1
N/A
POWER
DEFAULT
Refer to the AUXOBF1 description for information on this register.
Revision 1.1 (01-14-03)
146
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
