Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
UD
Read/Writeable by 8051. These bits are user-definable.
C/D
Command Data - This bit specifies whether the input data register contains data or a command (“0” =
data, “1” = command). During a host data/command write operation, this bit is set to "1" if SA2 = “1” or
reset to "0" if SA2 = 0.
IBF
Input Buffer Full - This flag is set to “1” whenever the host system writes data into the input data register.
Setting this flag activates the 8051's nIBF interrupt if enabled. When the 8051 reads the input data
register, this bit is automatically reset and the interrupt is cleared. There is no output pin associated
with this internal signal.
OBF
Output Buffer Full - This flag is set to “1” whenever the 8051 writes into the data registers at 7FF1H or
7FFAH. When the host system reads the output data register, this bit is automatically reset.
AUXOBF
Auxiliary Output Buffer Full - This flag is set to “1” whenever the 8051 writes into the data registers at
7FFAH. This flag is reset to “0” whenever the 8051 writes into the data registers at 7FF1H.
Table 13.7 PCOBF
HOST
N/A
8051
0x7FFD
VCC1
0x00
POWER
DEFAULT
Refer to the PCOBF description for information on this register. This is a “1” bit register (bits 1-7=0 on
read)
13.3
Host-to 8051 Keyboard Communication
The host system can send both commands and data to the KBD Data/Command Write register. The
CPU differentiates between commands and data by reading the value of bit 3 of the Status register.
When bit 3 is "1", the CPU interprets the register contents as a command. When Bit 3 is "0", the CPU
interprets the register contents as data. During a host write operation, bit 3 is set to "1" if SA2 = 1 or
reset to "0" if SA2 = 0.
13.3.1 PCOBF Description
(The following description assumes that OBFEN = 1 in Configuration Register 0); PCOBF is gated onto
KIRQ. The KIRQ signal is a system interrupt which signifies that the 8051 has written to the KBD Data
Read register via address 7FF1H. On power-up, PCOBF is reset to 0. PCOBF will normally reflect the
status of writes to 7FF1H, if PCOBFEN (bit 2 of Configuration register “0”) = “0”. (KIRQ is normally
selected as IRQ1 for keyboard support). PCOBF is cleared by hardware on a read of the Host Data
Register.
Additional flexibility has been added which allows firmware to directly control the PCOBF output signal,
independent of data transfers to the host-interface data output register. This feature allows the
LPC47N350 to be operated via the host "polled" mode. This firmware control is active when PCOBFEN
= 1 and firmware can then bring PCOBF high by writing a "1" to the LSB of the 1 bit data register,
PCOBF, allocated at 7FFDH. The firmware must also clear this bit by writing a "0" to the LSB of the 1
bit data register at 7FFDH.
SMSC LPC47N350
145
Revision 1.1 (01-14-03)
DATASHEET
SMSC [ SMSC CORPORATION ]
