Legacy-Free Keyboard/Embedded Controller with SPI and LPC Docking Interface
1 4 u s
6 u s
F E
S AEN
C om m and
K R E S ET
Pulse
C PU _R E SE T
From
K R E SE T
S peed up
Logic
G en
E N A B_P92
P ort92 R eg
nALT_R ST
1 4 u s
Bit 0
P ulse
G en
6 u s
Figure 13.2 CPU_Reset Implementation Diagram
13.4.3 Port 92
The LPC47N350 supports LPC I/O writes to port 92h as a quick alternate mechanism for generating a
CPU_RESET pulse or controlling the state of GATEA20.
Port 92 Register Description
D7-D2
D1
D0
HOST R/W
BIT DEF
R/W
0
R/W
ALT_GATEA20
R/W
ALT_CPU_RESET
Reserved
The Port92h register resides at host address 0x92 and is used to support the alternate reset
(nALT_RST) and alternate GATEA20 (ALT_A20) functions. This register defaults to 0x00 on assertion
of nRESET_OUT or on VCC2 Power On Reset.
Setting the Port 92 Enable bit (bit 0 of Logical Device 7 Configuration Register 0xF0) enables the
Port92h Register. When Port92 is disabled, by clearing the Port 92 Enable bit, then access to this
register is completely disabled (I/O writes to host 92h are ignored and I/O reads float the system data
bus SD[7:0]).
When Port92h is enabled the bits have the following meaning:
D7-D2 Reserved
A write are ignored and a read return 0.
ALT_GATEA20
This bit provides an alternate means for system control of the LPC47N350 GATEA20 pin.
= 0: ALT_A20 is driven low
= 1: ALT_A20 is driven high
When Port 92 is enabled, writing a 0 to bit 1 of the Port92 Register forces ALT_GATEA20 low.
ALT_GATEA20 low drives GATEA20 low, if A20 from the keyboard controller is also low. When Port 92
Revision 1.1 (01-14-03)
150
SMSC LPC47N350
DATASHEET
SMSC [ SMSC CORPORATION ]
