Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
VIH(AC) min
VREF to ac
region
V
IH(DC) min
nominal
slew rate
VREF(DC)
nominal slew
rate
VIL(DC) max
VREF to ac
region
VIL(AC) max
VSS
tVAC
∆ TF
∆ TR
V
REF(DC) - VIL(AC)max
Setup Slew Rate
Rising Signal
VIH(AC)min - VREF(DC)
Setup Slew Rate
Falling Signal
=
=
∆ TF
∆ TR
Figure 21. Illustration of nominal slew rate and tVAC for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock).
- 55 -
SAMSUNG [ SAMSUNG ]
