Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
nominal
line
V
IH(DC) min
dc to VREF
region
tangent
line
VREF(DC)
tangent
line
dc to VREF
region
nominal
line
VIL(DC) max
VIL(AC) max
VSS
∆ TF
∆ TR
tangent line [ VREF(DC) - VIL(DC)max ]
Hold Slew Rate
Rising Signal
=
∆ TR
tangent line [ VIH(DC)min - VREF(DC) ]
Hold Slew Rate
=
Falling Signal
∆ TF
Figure 24. Illustration of tangent line for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock)
- 58 -
SAMSUNG [ SAMSUNG ]
