Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
tVAC
nominal
line
VIH(AC) min
V
REF to ac
region
V
IH(DC) min
tangent
line
VREF(DC)
tangent
line
VIL(DC) max
VIL(AC) max
VREF to ac
region
nominal
line
∆ TR
tVAC
VSS
tangent line[VIH(AC)min - VREF(DC)]
Setup Slew Rate
Rising Signal
=
∆ TR
∆ TF
Setup Slew Rate tangent line[VREF(DC) - VIL(AC)max]
=
Falling Signal
∆ TF
Figure 23. Illustration of tangent line for setup time tDS (for DQ with respect to strobe) and tIS
(for ADD/CMD with respect to clock)
- 57 -
SAMSUNG [ SAMSUNG ]
