Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
14.3 Address/Command Setup, Hold and Derating :
For all input signals the total tIS (setup time) and tIH (hold time) required is calculated by adding the data sheet tIS(base) and tIH(base) value (see
Table 50) to the ∆tIS and ∆tIH derating value (see Table 51) respectively.
Example: tIS (total setup time) = tIS(base) + ∆tIS Setup (tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
V
REF(DC) and the first crossing of VIH(AC)min. Setup (tIS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of
VREF(DC) and the first crossing of VIL(AC)max. If the actual signal is always earlier than the nominal slew rate line between shaded ’VREF(DC) to ac
region’, use nominal slew rate for derating value (see Figure 21). If the actual signal is later than the nominal slew rate line anywhere between shaded
’VREF(DC) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for derating value (see Figure 23).
Hold (tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VIL(DC)max and the first crossing of VREF(DC).
Hold (tIH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VIH(DC)min and the first crossing of VREF(DC). If
the actual signal is always later than the nominal slew rate line between shaded ’dc to VREF(DC) region’, use nominal slew rate for derating value (see
Figure 22). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ’dc to VREF(DC) region’, the slew rate of a tangent line
to the actual signal from the dc level to VREF(DC) level is used for derating value (see Figure 24).
For a valid transition the input signal has to remain above/below VIH/IL(AC) for some time tVAC (see Table 51).
Although for slow slew rates the total setup time might be negative (i.e. a valid input signal will not have reached VIH/IL(AC) at the time of the rising clock
transition) a valid input signal is still required to complete the transition and reach VIH/IL(AC).
For slew rates in between the values listed in Table 51, the derating values may obtained by linear interpolation.
These values are typically not subject to production test. They are verified by design and characterization.
[ Table 50 ] ADD/CMD Setup and Hold Base-Values for 1V/ns
[ps]
DDR3L-800
215
DDR3L-1066
DDR3L-1333
DDR3L-1600
reference
VIH/L(AC)
VIH/L(AC)
VIH/L(DC)
tIS(base) AC160
tIS(base) AC135
tIH(base)-DC90
140
290
210
80
60
365
205
150
185
130
285
NOTE :
1. AC/DC referenced for 1V/ns Address/Command slew rate and 2 V/ns differential CK-Ck slew rate
2. The tIS(base) AC135 specifications are adjusted from the tIS(base) AC160 specification by adding an additional 125ps for DDR3L-800/1066 or 100ps for DDR3L-1333/1600
of derating to accommodate for the lower alternate threshold of 135mV and another 25ps to account for the earlier reference point [(160mV-135mV)/1 V/ns]
[ Table 51 ] Derating values DDR3-800/1066/1333/1600 tIS/tIH-AC/DC based
∆tIS, ∆tIH Derating [ps] AC/DC based
AC175 Threshold -> VIH(AC) = VREF(DC) + 175mV, VIL(AC) = VREF(DC) - 175mV
CLK,CLK Differential Slew Rate
4.0 V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4V/ns
1.2V/ns
∆tIS
1.0V/ns
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
50
∆tIS
∆tIH
58
42
8
∆tIS
∆tIH
66
50
16
12
6
∆tIS
∆tIH
74
58
24
20
14
8
∆tIH
84
68
34
30
24
18
8
∆tIS
∆tIH
100
84
2.0
1.5
1.0
0.9
0.8
0.7
0.6
0.5
0.4
88
59
0
88
59
0
88
59
0
96
67
8
104
75
16
14
10
5
112
83
24
22
18
13
7
120
91
32
30
26
21
15
-2
128
99
40
38
34
29
23
5
34
34
34
0
0
0
50
CMD/
ADD
Slew
rate
-2
-4
-2
-4
-2
-4
6
4
46
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
-6
-10
-16
-26
-40
-60
2
-2
40
-11
-17
-35
-62
-11
-17
-35
-62
-11
-17
-35
-62
-3
-9
-27
-54
-8
0
34
V/ns
-18
-32
-52
-1
-10
-24
-44
-2
24
-19
-46
-11
-38
-16
-36
-6
10
-30
-26
-22
-10
- 53 -
SAMSUNG [ SAMSUNG ]
