Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
NOTE :Clock and Strobe are drawn on a different time scale.
tIH
tIH
tIS
tIS
CK
CK
DQS
DQS
tDH
tDH
tDS
tDS
VDDQ
VIH(AC) min
V
IH(DC) min
dc to VREF
region
nominal
slew rate
VREF(DC)
nominal
dc to VREF
region
slew rate
VIL(DC) max
VIL(AC) max
VSS
∆ TR
∆ TF
Hold Slew Rate
Rising Signal
V
REF(DC) - VIL(DC)max
Hold Slew Rate
Falling Signal
V
IH(DC)min - VREF(DC)
=
=
∆ TR
∆ TF
Figure 22. Illustration of nominal slew rate for hold time tDH (for DQ with respect to strobe) and tIH
(for ADD/CMD with respect to clock).
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SAMSUNG [ SAMSUNG ]
