Rev. 1.01
K4B2G0446D
K4B2G0846D
datasheet
DDR3L SDRAM
[ Table 49 ] Timing Parameters by Speed Bin (Cont.)
Speed
DDR3-800
DDR3-1066
DDR3-1333
DDR3-1600
Units
NOTE
Parameter
Symbol
MIN
MAX
MIN
MAX
MIN
MAX
MIN
MAX
Data Strobe Timing
DQS, DQS differential READ Preamble
DQS, DQS differential READ Postamble
DQS, DQS differential output high time
DQS, DQS differential output low time
DQS, DQS differential WRITE Preamble
DQS, DQS differential WRITE Postamble
tRPRE
tRPST
tQSH
0.9
0.3
Note 19
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
0.9
0.3
0.4
0.4
0.9
0.3
Note 19
tCK
tCK
13, 19, g
11, 13, b
13, g
Note 11
Note 11
Note 11
Note 11
0.38
0.38
0.9
-
-
-
-
0.38
0.38
0.9
-
-
-
-
-
-
-
-
-
-
-
-
tCK(avg)
tCK(avg)
tCK
tQSL
13, g
tWPRE
tWPST
0.3
0.3
tCK
DQS, DQS rising edge output access time from rising
CK, CK
tDQSCK
tLZ(DQS)
tHZ(DQS)
-400
-800
-
400
400
400
-300
-600
-
300
300
300
-255
-500
-
255
250
250
-225
-450
-
225
225
225
ps
ps
ps
13,f
DQS, DQS low-impedance time (Referenced from RL-
1)
13,14,f
12,13,14
DQS, DQS high-impedance time (Referenced from
RL+BL/2)
DQS, DQS differential input low pulse width
DQS, DQS differential input high pulse width
DQS, DQS rising edge to CK, CK rising edge
DQS,DQS falling edge setup time to CK, CK rising edge
DQS,DQS falling edge hold time to CK, CK rising edge
Command and Address Timing
tDQSL
tDQSH
tDQSS
tDSS
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.25
0.2
0.55
0.55
0.25
-
0.45
0.45
-0.27
0.18
0.18
0.55
0.55
0.27
-
tCK
29, 31
30, 31
c
tCK
tCK(avg)
tCK(avg)
tCK(avg)
c, 32
c, 32
tDSH
0.2
-
0.2
-
0.2
-
-
DLL locking time
tDLLK
tRTP
512
-
-
512
-
-
512
-
-
512
-
-
nCK
internal READ Command to PRECHARGE Command
delay
max
max
max
max
e
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
Delay from start of internal write transaction to internal
read command
max
max
max
max
tWTR
-
-
-
-
e,18
e
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
WRITE recovery time
tWR
15
4
-
-
15
4
-
-
15
4
-
-
15
4
-
-
ns
Mode Register Set command cycle time
tMRD
nCK
max
max
max
max
Mode Register Set command update delay
tMOD
-
-
-
-
-
-
-
(12nCK,15ns)
(12nCK,15ns)
(12nCK,15ns)
(12nCK,15ns)
CAS# to CAS# command delay
tCCD
tDAL(min)
tMPRR
tRAS
4
4
-
4
4
nCK
nCK
nCK
ns
Auto precharge write recovery + precharge time
Multi-Purpose Register Recovery Time
ACTIVE to PRECHARGE command period
WR + roundup (tRP / tCK(AVG))
1
-
1
-
1
-
1
-
22
e
See “Speed Bins and CL, tRCD, tRP, tRC and tRAS for corresponding Bin”
max
max
max
max
ACTIVE to ACTIVE command period for 1KB page size
ACTIVE to ACTIVE command period for 2KB page size
tRRD
tRRD
-
-
-
-
-
-
-
-
e
e
(4nCK,10ns)
(4nCK,7.5ns)
(4nCK,6ns)
(4nCK,6ns)
max
max
max
max
(4nCK,10ns)
(4nCK,10ns)
(4nCK,7.5ns)
(4nCK,7.5ns)
Four activate window for 1KB page size
Four activate window for 2KB page size
tFAW
tFAW
40
50
-
-
37.5
50
-
-
30
45
-
-
30
40
-
-
ns
ns
e
e
1.35V
tIS(base)
AC160
215
200
285
275
365
140
125
210
200
290
80
1.5V
65
-
-
-
60
45
-
-
-
-
-
ps
ps
ps
ps
ps
b,16
b,16
-
-
-
-
-
-
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
tIS(base)
AC175
1.35V
150
tIH(base)
DC90
130
120
185
b,16
Command and Address hold time from CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
1.5V
140
tIH(base)
DC100
b,16
1.35V
205
tIS(base)
AC135
-
b,16,27
-
-
Command and Address setup time to CK, CK refer-
enced to V (AC) / V (AC) levels
IH
IL
1.5V
190
tIS(base)
AC150
350
900
275
780
-
-
170
560
-
-
ps
ps
b,16,27
28
-
-
-
-
Control & Address Input pulse width for each input
Calibration Timing
tIPW
620
Power-up and RESET calibration time
Normal operation Full calibration time
Normal operation short calibration time
tZQinitI
tZQoper
tZQCS
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
512
256
64
-
-
-
nCK
nCK
nCK
23
- 49 -
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