RT8859M
When the CORE VR receives SetPS command of PS2
operation mode, the CORE VR operates as a single phase
DCM controller, and only channel 1 is active with diode
emulation operation. The CORE VR will disable phase 2,
phase 3 and phase 4 by disabling Internal PWM logic
drivers at PWM2, PWM3 and PWM4 pins (PWM = high
impedance state). Therefore, 4 external drivers which
support tri-state shutdown are required for compatibility
with PS2 operation state.
Ramp Amplitude Adjust
When the CORE VR enters PS2 operation mode, the
internal ramp of CORE VR will be modified for the reason
of stability. In case of smooth transition into PS2, the
CCM ramp amplitude should be designed properly. The
RT8859M provides RSET pin for platform users to set the
ramp amplitude of the CORE VR in CCM. The criteria is
to set the ramp amplitude proportional to the on-time (when
VDAC < 1.2V). The equation will be :
57.6 x 10−12 = tON x (VIN − VDAC) x 1/RSET
where 57.6 x 10−12 is an internal coefficient of analog
circuit.
(21)
If the CORE VR receives dynamic VIDchange command
(SetVID), the CORE VR will automatically enter PS0
operation mode and all phases will be activated. After
VOUT,CORE reaches target voltage, the CORE VR will stay
at PS0 state and ignore former SetPS command. Only
re-sending SetPS command after SetVID command will
the CORE VR be forced into PS1 or PS2 operation states
again.
According to equation (12), the RSET equation can be
simplified to :
RRSET = 0.4236 x RTON
(22)
Thermal Monitoring and Temperature Reporting
Dynamic VID Enhancement
The CORE VR provides thermal monitoring function via
sensing TSEN pin voltage. Through the voltage divider
resistors, R1 and RNTC, the voltage of TSEN will be
proportional to VR temperature. When VR temperature
rises, TSEN voltage also rises. The ADC circuit of the
CORE VR monitors the voltage variation at the TSEN pin
from 1.46V to 1.845V with 55mV resolution. This voltage
is then decoded into digital format and stored into
Temperature_Zone register.
During a dynamic VID event, the charging (dynamic VID
up) or discharging (dynamic VID down) current causes
unwanted load-line effect which degrades the settling time
performance. The DVID pin can be used to compensate
the load-line effect, so that the output voltage can settle
to the target value more quickly.
During a dynamic VID up event, the RT8859M sources
out a current (IDVID) to DVID pin. The voltage on DVID pin
is added toDAC duringDVIDrising to enhance the dynamic
VID performance. Connecting a capacitor in parallel with
a resistor to DVID pin is recommended.
V
CC
R2
NTC
TSEN
IDVID is 8μA during a SetVID_Fast event. If it is a
SetVID_Slow event, IDVID automatically shrinks to 2μA(if
slow slew rate is 0.25x fast slew rate) or 4μA(if slow slew
rate is 0.5x fast slew rate). This function is null during a
dynamic VIDdown event.
R1
Figure 11. CORE VR : Thermal Monitoring Circuit
To meet Intel's VR12/IMVP7 specification, platform users
have to set the TSEN voltage to meet the temperature
variation of VR from 75% to 100% VR max temperature.
For example, if the VR max temperature is 100°C, platform
users have to set the TSEN voltage to be 1.515V when
VR temperature reaches 82°C and 1.845V when VR
temperature reaches 100°C. Detailed voltage setting
versus temperature variation is shown in Table 5. The
thermometer code is implemented in Temperature_Zone
register.
DAC
I
DVID
Slew Rate
Control
DVID
Event
DVID
FB
1/20
+
EA
-
Figure 10.DVIDCompensation Circuit
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
www.richtek.com
37
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