RT8859M
V
IN, CORE
CORE VR
V
OUT, CORE
HS_FET
CCRCOT
PWM
Logic
L
Active Phase Determination : Before POR
PWMx
Driver
R
X
C
X
CMP
R
C
The number of active phases is determined by the internal
circuitry that monitors the ISENxN voltages during start-
up. Normally, the CORE VR operates as a 4-phase PWM
controller. Pulling ISEN4N to VCC programs a 3-phase
operation, pulling ISEN3Nand ISEN4Nto VCC programs
a 2-phase operation, and pulling ISEN2N, ISEN3N and
ISEN4N to VCC programs a 1-phase operation. Before
POR, CORE VR detects whether the voltages of ISEN2N,
ISEN3N and ISEN4N are higher than “VCC − 1V”
respectively to decide how many phases should be active.
Phase selection is only active during POR. When POR =
high, the number of active phases is determined and
latched. The unused ISENxP pins are recommended to
be connected to VCC and unused PWM pins can be left
floating.
LS_FET
C
ISENxP
ISENxN
+
A
I
V
CS
-
C1
R1
C2
R2
Offset
Canceling
COMP
V
CC_SENSE
FB
-
EA
RGND
V
+
SS_SENSE
V
DAC, CORE
Figure 5. CORE VR : Simplified Schematic for Droop
and Remote Sense in CCM
Droop Setting (with Temperature Compensation)
It's very easy to achieveActive Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
V
OUT = VDAC − ILOAD x RDROOP
(1)
Loop Control
Then solving the switching condition VCOMP2 = VCS in
Figure 5 yields the desired error amplifier gain as
The CORE VR adopts Richtek's proprietary G-NAVPTM
topology.G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VOUT, CORE, will
decrease with increasing output load current. The control
loop consists of PWM modulators with power stages,
current sense amplifiers and an error amplifier as shown
in Figure 5.
A ×R
R2
R1
I
SENSE
A
=
=
(2)
V
R
DROOP
whereAI is the internal current sense amplifier gain. RSENSE
is the current sense resistor. If no external sense resistor
present, it is the DCR of the inductor. RDROOP is the
equivalent load line resistance as well as the desired static
output impedance.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMP voltage also
increases and induces VOUT, CORE to decrease, thus
achievingAVP. Anear-DC offset canceling is added to the
output of EA to eliminate the inherent output offset of finite
gain peak current mode controller.
V
OUT
A
> A
V1
V2
A
A
V2
V1
0
Load Current
Figure 6. CORE VR : ErrorAmplifier gain (AV) Influence
on VOUT Accuracy
Since theDCR of the inductor is temperature dependent,
it affects the output accuracy at hot conditions.
Temperature compensation is recommended for the
lossless inductor DCR current sense method. Figure 7
shows a simple but effective way of compensating the
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
www.richtek.com
33
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
