RT8859M
and ISENxNdenote the positive and negative input of the
current sense amplifier of any phase.
implemented through the SVIDinterface or OFS pin. Users
can disable pin offset function by simply connecting OFS
pin toGND. The RT8859M will latch the OFS status after
POR.
Users can either use a current sense resistor or the
inductor's DCR for current sensing. Using the inductor's
DCR allows higher efficiency as shown in Figure 9. Refer
If pin offset function is enabled, users can decide whether
to disable SVID OFS or not by selecting proper resistor
values of ICCMAX pin. After receiving a valid VID, the
RT8859M sinks in 16μA from ICCMAX pin. The voltage on
to below equation for optimum transient performance :
L
= R × C
(15)
X
X
DCR
0.36μH
1mΩ x 100nF
(16)
ICCMAX is
R
=
= 3.6kΩ
X
R2
R1 + R2
(17)
(18)
V
=
x VCC − 16μA (R1//R2)
ICCMAX
V
OUT, CORE
If VICCMAX <1V, then the output voltage is
VOUT = VDAC − ILOAD x RDROOP + VPIN−OFS
If VICCMAX >1V, then the output voltage is
L
DCR
C
X
R
X
+ V
-
X
ISENxP
ISENxN
V
= V
− I
x R
+ V
OUT
DAC
LOAD
DROOP PIN−OFS
(19)
+ V
SVID−OFS
The pin offset voltage is set by supplying a voltage into
OFS pin. The linear range of offset pin voltage is from
0.9V to 1.83V. The pin offset voltage can be calculated as
below :
Figure 9. CORE VR : Lossless Inductor Sensing
Considering the inductance tolerance, the resistor RX has
to be tuned on board by examining the transient voltage.
If the output voltage transient has an initial dip below the
minimum load line requirement with a slow recovery, RX
is chosen too small. Vice versa, with a resistance too
large the output voltage transient has only a small initial
dip and the recovery is too fast causing a ring back.
VPIN−OFS = VOFS − 1.2V
(20)
For example, supplying 1.3V at OFS pin will achieve
100mV offset at the output. Connecting a filter capacitor
between the OFS pin and GND is necessary. Designers
can design the offset slew rate by properly setting the
filter bandwidth.
Using current sense resistor in series with the inductor
can have better accuracy, but the efficiency is a trade-off.
Considering the equivalent inductance (LESL) of the current
sense resistor, an RC filter is recommended. The RC filter
calculation method is similar to the above mentioned
inductorDCR sensing method.
Operation Mode Transition
RT8859M supports operation mode transition function at
the CORE VR for the SetPS command of Intel's VR12/
IMVP7 CPU. The default operation mode of the CORE
VR is PS0, which is full phase CCM operation. Other
operation modes includes PS1 (single phase CCM
operation) and PS2 (single phaseDEM operation).
Current Balance
The CORE VR implements internal current balance
mechanism in the current loop. The CORE VR senses
and compares per-phase current signal with average
current. If the sensed current of any particular phase is
larger than average current, the on-time of this phase will
be adjusted to be shorter.
After receiving SetPS command, the CORE VR will
immediately change to the new operation state. When
the CORE VR receives SetPS command of PS1 operation
mode, the CORE VR operates as a single phase CCM
controller, and only channel 1 is active. The CORE VR will
disable phase 2, phase 3 and phase 4 by disabling Internal
PWM logic drivers at PWM2, PWM3 and PWM4 pins
(PWM = high impedance state). Therefore, 3 external
drivers which support tri-state shutdown are required for
compatibility with PS1 operation mode.
No Load Offset (SVID & Platform)
The CORE VR features no load offset function which
provides the possibility of wide range positive offset of
output voltage. The no-load offset function can be
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
36
DS8859M-05 July 2012
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
