RT8859M
V
IN, AXG
by 300mV, the CORE VR will trigger UVP latch. The UVP
latch will turn off both high side and low side MOSFETs.
When UVP is triggered by the CORE VR, the AXG VR
will also enter soft shut down sequence. A 3μs delay is
used in UVP detection circuit to prevent false trigger. If
platform OFS function is enabled (OFS pin not connected
to GND), the UVP function will be disabled.
V
OUT, AXG
HS_FET
CCRCOT
PWM
Logic
L
PWMA
Driver
R
X
C
X
R
C
CMP
LS_FET
C
ISENAP
ISENAN
+
A
I
V
CS
-
C1
R1
C2
Offset
Canceling
R2
COMPA
V
Under Voltage Lock Out (UVLO)
CCAXG_SENSE
FBA
-
EA
During normal operation, if the voltage at the VCC orDVD
pin drops below POR threshold, the CORE VR will trigger
UVLO. The UVLO protection forces all high side MOSFETs
and low side MOSFETs off by shutting down internal PWM
logic drivers.A3μs delay is used in UVLO detection circuit
to prevent false trigger.
RGNDA
V
+
SSAXG_SENSE
V
DAC, AXG
Figure 16. AXGVR : Simplified Schematic for Droop and
Remote Sense in CCM
Droop Setting (with Temperature Compensation)
It's very easy to achieveActive Voltage Positioning (AVP)
by properly setting the error amplifier gain due to the native
droop characteristics. The target is to have
AXG VR
AXG VR Disable
TheAXGVR can be disabled by connecting ISENANto a
voltage higher than “VCC − 1V”. If not in use, ISENAP,
TSENA and DVDA are recommended to be connected to
VCC, while PWMA is left floating. When AXG VR is
disabled, all SVID commands related to AXG VR will be
rejected.
VOUTAXG = VDACAXG − ILOAD x RDROOP
(38)
, then solving the switching condition VCOMP2 = VCS in
Figure 16 yields the desired error amplifier gain as
A x R
R
R2
R1
I
SENSE
DROOP
(39)
A
=
=
V
whereAI is the internal current sense amplifier gain, RSENSE
is the current sense resistance (an external sense resistor
or theDCR of the inductor), and RDROOP is the equivalent
load line resistance as well as the desired static output
impedance.
Loop Control
The AXG VR adopts Richtek's proprietary G-NAVPTM
topology.G-NAVPTM is based on the finite gain peak current
mode with CCRCOT (Constant Current Ripple Constant
On-Time) topology. The output voltage, VOUT, AXG, will
decrease with increasing output load current. The control
loop consists of a PWM modulator with power stage, a
current sense amplifier and an error amplifier as shown in
Figure 16.
Since theDCR of the inductor is temperature dependent,
the output accuracy may be affected at high temperature
conditions. Temperature compensation is recommended
for the lossless inductor DCR current sense method.
Figure 17 shows a simple but effective way of
compensating the temperature variations of the sense
resistor by using anNTC thermistor placed in the feedback
path.
Similar to the peak current mode control with finite
compensator gain, the HS_FET on-time is determined by
CCRCOT on-time generator. When load current increases,
VCS increases, the steady state COMPA voltage also
increases and induces VOUT,AXG to decrease, thus achieving
AVP. Anear-DC offset canceling is added to the output of
EAto cancel the inherent output offset of finite-gain peak
current mode controller.
C2
C1
R2
R1a
R1b
COMPA
V
CCAXG_SENSE
FBA
R
NTC
-
EA
RGNDA
V
+
SSAXG_SENSE
V
DAC,AXG
Figure 17. AXGVR : Loop Setting with Temperature
Compensation
Copyright 2012 Richtek Technology Corporation. All rights reserved.
©
is a registered trademark of Richtek Technology Corporation.
DS8859M-05 July 2012
www.richtek.com
41
RICHTEK [ RICHTEK TECHNOLOGY CORPORATION ]
