MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
“0”
“1” BSEL0
7
0
I2C control register
(S1D : address 00F916)
SCL1/P11
SCL2/P12
SDA1/P13
SDA2/P14
10 BIT
SAD
BSEL1 BSEL0
ALS ES0 BC2 BC1 BC0
“0”
“1” BSEL1
SCL
Multi-master
I2C-BUS
interface
Bit counter (Number of
transmit/receive bits)
b2 b1 b0
“0”
“1” BSEL0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
: 8
: 7
: 6
: 5
: 4
: 3
: 2
: 1
“0”
“1” BSEL1
SDA
Note: When using multi-master I2C-BUS interface,
set bits 3 and 4 of the serial I/O mode register
(address 021316) to “1.”
I2C-BUS interface use
enable bit
0 : Disabled
1 : Enabled
Fig. 39. Connection port control by BSEL0 and BSEL1
Data format selection bit
0 : Addressing format
1 : Free data format
2
2
(5) I C Status Register
2
The I C status register (address 00F816) controls the I C-BUS inter-
face status. The low-order 4 bits are read-only bits and the high-
order 4 bits can be read out and written to.
Addressing format
selection bit
0 : 7-bit addressing
format
1 : 10-bit addressing
format
■ Bit 0: Last receive bit (LRB)
This bit stores the last bit value of received data and can also be
used for ACK receive confirmation. If ACK is returned when an ACK
clock occurs, the LRB bit is set to “0.” If ACK is not returned, this bit
is set to “1.” Except in the ACK mode, the last bit value of received
data is input. The state of this bit is changed from “1” to “0” by execut-
Connection control bits
between I2C-BUS
interface and ports
2
ing a write instruction to the I C data shift register (address 00F616).
b7 b6 Connection port
■ Bit 1: General call detecting flag (AD0)
0
0
1
1
0 : None
This bit is set to “1” when a general call✽ whose address data is all “0”
is received in the slave mode. By a general call of the master device,
every slave device receives control data after the general call. The
AD0 bit is set to “0” by detecting the STOP condition or START con-
dition.
SCL1, SDA1
1 :
0 : SCL2, SDA2
1 : SCL1, SDA1,
SCL2, SDA2
2
Fig. 40. Structure of I C control register
✽General call: The master transmits the general call address “0016”
to all slaves.
■ Bit 2: Slave address comparison flag (AAS)
This flag indicates a comparison result of address data.
➀In the slave receive mode, when the 7-bit addressing format is
selected, this bit is set to “1” in one of the following conditions.
The address data immediately after occurrence of a START
•
condition agrees with the slave address stored in the high-order
2
7 bits of the I C address register (address 00F716).
A general call is received.
•
➁In the slave reception mode, when the 10-bit addressing format is
selected, this bit is set to “1” with the following condition.
2
When the address data is compared with the I C address
•
register (8 bits consisted of slave address and RBW), the first
bytes agree.
➂ The state of this bit is changed from “1” to “0” by executing a write
2
instruction to the I C data shift register (address 00F616).
39
RENESAS [ RENESAS TECHNOLOGY CORP ]
