MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(9) Address Data Communication
(8) START/STOP Condition Detecting Condi-
There are two address data communication formats, namely, 7-bit
tions
addressing format and 10-bit addressing format. The respective ad-
dress communication formats is described below.
➀ 7-bit addressing format
The START/STOP condition detecting conditions are shown in Fig-
ure 45 and Table 9. Only when the 3 conditions of Table 9 are satis-
fied, a START/STOP condition can be detected.
To meet the 7-bit addressing format, set the 10BIT SAD bit of the
2
I C control register (address 00F916) to “0.” The first 7-bit address
Note: When a STOP condition is detected in the slave mode
(MST = 0), an interrupt request signal “IICIRQ” occurs to the
CPU.
data transmitted from the master is compared with the high-order
2
7-bit slave address stored in the I C address register (address
00F716). At the time of this comparison, address comparison of
2
the RBW bit of the I C address register (address 00F716) is not
SCL release time
made. For the data transmission format when the 7-bit address-
ing format is selected, refer to Figure 46, (1) and (2).
➁ 10-bit addressing format
SCL
Setup
Hold time
time
SDA
To meet the 10-bit addressing format, set the 10BIT SAD bit of the
(START condition)
Setup
2
Hold time
time
I C control register (address 00F916) to “1.” An address compari-
SDA
(STOP condition)
son is made between the first-byte address data transmitted from
2
the master and the 7-bit slave address stored in the I C address
register (address 00F716). At the time of this comparison, an ad-
2
Fig. 45. START condition/STOP condition detecting timing
diagram
dress comparison between the RBW bit of the I C address regis-
ter (address 00F716) and the R/W bit which is the last bit of the
address data transmitted from the master is made. In the 10-bit
addressing mode, the R/W bit which is the last bit of the address
data not only specifies the direction of communication for control
data but also is processed as an address data bit.
Table 9. START condition/STOP condition detecting conditions
High-speed clock mode
Standard clock mode
1.0 µs (4 cycles) < SCL
6.5 µs (26 cycles) < SCL
release time
release time
0.5 µs (2 cycles) < Setup time
0.5 µs (2 cycles) < Hold time
3.25 µs (13 cycles) < Setup time
3.25 µs (13 cycles) < Hold time
Note: Absolute time at φ = 4 MHz. The value in parentheses de-
notes the number of φ cycles.
S
Slave address R/W
7 bits “0”
A
Data
A
Data
A/A
P
P
1 to 8 bits
1 to 8 bits
(1) A master-transmitter transmits data to a slave-receiver
S
Slave address R/W
7 bits “1”
A
Data
A
Data
A
1 to 8 bits
1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
Slave address
1st 7 bits
Slave address
2nd byte
S
R/W
“0”
A
A
Data
1 to 8 bits
A
Data
A/A
P
7 bits
8 bits
1 to 8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
Slave address
1st 7 bits
Slave address
2nd byte
Slave address
1st 7 bits
S
R/W
“0”
A
A
Sr
R/W
Data
A
Data
A
P
7 bits
8 bits
7 bits
“1” 1 to 8 bits
1 to 8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
From master to slave
From slave to master
Fig. 46. Address data communication format
42
RENESAS [ RENESAS TECHNOLOGY CORP ]
