MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(12) Synchronizing Signal Counter
The synchronizing signal counter counts the composite sync signal
taken out from a video signal in the data slicer circuit or the vertical
synchronizing signal Vsep as a count source.
7
0
Sync pulse counter register
(SYC : address 00EA16)
13
The count value in a certain time (T time) generated by f(XIN)/2 or
13
Count value
Count time
f(XIN)/2 is stored into the 5-bit latch. Accordingly, the latch value
changes in the cycle of T time. When the count value exceeds “1F16,”
“1F16” is stored into the latch.
Count source
The latch value can be obtained by reading out the sync pulse counter
register (address 00EA16). A count source is selected by bit 5 of the
sync pulse counter register.
0: HSYNC
signal
f(XIN)/213
(1024 s, f(XIN) = 8 MHz)
The synchronizing signal counter is used when bit 0 of the PWM
mode register 1 (address 02EA16).
1: Composite
sync signal
Figure 34 shows the structure of the sync pulse counter and Figure
35 shows the synchronizing signal counter block diagram.
Fig. 34. Sync pulse counter register
f(XIN)/213
Composite
sync signal
Reset
Counter
5-bit counter
HSYNC signal
Sync pulse
counter register
Latch (5 bits)
b5
Selection gate : connected to black
colored side when
reset.
Data bus
Fig. 35. Synchronizing signal counter block diagram
35
RENESAS [ RENESAS TECHNOLOGY CORP ]
