MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
(6) START Condition Generating Method
2
7
0
When the ES0 bit of the I C control register (address 00F916) is “1,”
I2C status register
(S1 : address 00F816
2
execute a write instruction to the I C status register (address 00F816)
MST TRX BB PIN AL AAS AD0 LRB
)
for setting the MST, TRX and BB bits to “1.” Then a START condi-
tion occurs. After that, the bit counter becomes “0002” and an SCL
for 1 byte is output. The START condition generating timing and BB
bit set timing are different in the standard clock mode and the high-
speed clock mode. Refer to Figure 43, the START condition generat-
ing timing diagram, and Table 8, the START condition/STOP condi-
tion generating timing table.
Last receive bit (Note)
0 : Last bit = “0”
1 : Last bit = “1”
General call detecting flag
(Note)
0 : No general call detected
1 : General call detected
Slave address comparison flag
(Note)
0 : Address disagreement
1 : Address agreement
I2C status register
write signal
SCL
Setup
Hold time
time
Arbitration lost detecting flag
(Note)
0 : Not detected
1 : Detected
SDA
Set time for
BB flag
BB flag
Setup
time
I2C-BUS interface interrupt
request bit
0 : Interrupt request issued
1 : No interrupt request
issued
Fig. 43. START condition generating timing diagram
(7) STOP Condition Generating Method
2
Bus busy flag
0 : Bus free
1 : Bus busy
When the ES0 bit of the I C control register (address 00F916) is “1,”
2
execute a write instruction to the I C status register (address 00F816)
for setting the MST bit and the TRX bit to “1” and the BB bit to “0”.
Then a STOP condition occurs. The STOP condition generating tim-
ing and the BB flag reset timing are different in the standard clock
mode and the high-speed clock mode. Refer to Figure 44, the STOP
condition generating timing diagram, and Table 8, the START condi-
tion/STOP condition generating timing table.
Communication mode
specification bits
00 : Slave receive mode
01 : Slave transmit mode
10 : Master receive mode
11 : Master transmit mode
Note: These bit and flags can be read out but cannot
be written.
I2C status register
write signal
2
Fig. 41. Structure of I C status register
SCL
Setup
time
Hold time
SDA
Reset time for
BB flag
BB flag
SCL
PIN
Fig. 44. STOP condition generating timing diagram
Table 8. START condition/STOP condition generating timing
table
IICIRQ
Item
Setup time
Hold time
Standard clock mode High-speed clock mode
5.0 µs (20 cycles)
5.0 µs (20 cycles)
2.5 µs (10 cycles)
2.5 µs (10 cycles)
Fig. 42. Interrupt request signal generating timing
Set/reset time
for BB flag
3.0 µs (12 cycles)
1.5 µs (6 cycles)
Note: Absolute time at φ = 4 MHz. The value in parentheses de-
notes the number of φ cycles.
41
RENESAS [ RENESAS TECHNOLOGY CORP ]
