MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
■ Bit 3: Arbitration lost✽ detecting flag (AL)
mitted by the master is “1.” When the ALS bit is “0” and the R/W bit is
In the master transmission mode, when the SDA is made “L” by any
other device, arbitration is judged to have been lost, so that this bit is
set to “1.” At the same time, the TRX bit is set to “0,” so that immedi-
ately after transmission of the byte whose arbitration was lost is com-
pleted, the MST bit is set to “0.” In the case arbitration is lost during
slave address transmission, the TRX bit is set to “0” and the recep-
tion mode is set. Consequently, it becomes possible to receive and
recognize its own slave address transmitted by another master de-
vice.
“0,” the TRX bit is cleared to “0” (receive).
The TRX bit is cleared to “0” in one of the following conditions.
When arbitration lost is detected.
•
When a STOP condition is detected.
•
When occurence of a START condition is disabled by the START
•
condition duplication preventing function (Note).
With MST = “0” and when a START condition is detected.
•
With MST = “0” and when ACK non-return is detected.
•
At reset
•
■ Bit 7: Communication mode specification bit (master/slave speci-
fication bit: MST)
✽Arbitration lost: The status in which communication as a master is
disabled.
This bit is used for master/slave specification for data communica-
tion. When this bit is “0,” the slave is specified, so that a START
condition and a STOP condition generated by the master are re-
ceived, and data communication is performed in synchronization with
the clock generated by the master. When this bit is “1,” the master is
specified and a START condition and a STOP condition are gener-
ated, and also the clocks required for data communication are gen-
erated on the SCL.
2
■ Bit 4: I C-BUS interface interrupt request bit (PIN)
This bit generates an interrupt request signal. Each time 1-byte data
is transmitted, the state of the PIN bit changes from “1” to “0.” At the
same time, an interrupt request signal occurs to the CPU. The PIN
bit is set to “0” in synchronization with a falling of the last clock (in-
cluding the ACK clock) of an internal clock and an interrupt request
signal occurs in synchronization with a falling of the PIN bit. When
the PIN bit is “0,” the SCL is kept in the “0” state and clock generation
is disabled. Figure 42 shows an interrupt request signal generating
timing chart.
The MST bit is cleared to “0” in one of the following conditions.
Immediately after completion of 1-byte data transmission when ar-
•
bitration lost is detected
The PIN bit is set to “1” in one of the following conditions.
When a STOP condition is detected.
•
•
2
Executing a write instruction to the I C data shift register (address
•
When occurence of a START condition is disabled by the START
00F616).
condition duplication preventing function (Note).
When the ES0 bit is “0”
•
•
At reset
•
At reset
The conditions in which the PIN bit is set to “0” are shown below:
Note: The START condition duplication prevention function disables
the occurence of a START condition, reset of bit counter and
SCL output when the following condition is satisfied:
Immediately after completion of 1-byte data transmission (includ-
•
ing when arbitration lost is detected)
Immediately after completion of 1-byte data reception
•
•
• a START condition is set by another master device.
In the slave reception mode, with ALS = “0” and immediately after
completion of slave address or general call address reception
In the slave reception mode, with ALS = “1” and immediately after
•
completion of address data reception
■ Bit 5: Bus busy flag (BB)
This bit indicates the status of use of the bus system. When this bit is
set to “0,” this bus system is not busy and a START condition can be
generated. When this bit is set to “1,” this bus system is busy and the
occurrence of a START condition is disabled by the START condi-
tion duplication prevention function (Note).
This flag can be written by software only in the master transmission
mode. In the other modes, this bit is set to “1” by detecting a START
condition and set to “0” by detecting a STOP condition. When the
2
ES0 bit of the I C control register (address 00F916) is “0” and at
reset, the BB flag is kept in the “0” state.
■ Bit 6: Communication mode specification bit (transfer direction
specification bit: TRX)
This bit decides a direction of transfer for data communication. When
this bit is “0,” the reception mode is selected and the data of a trans-
mitting device is received. When the bit is “1,” the transmission mode
is selected and address data and control data are output onto the
SDA in synchronization with the clock generated on the SCL.
2
When the ALS bit of the I C control register (address 00F916) is “0”
in the slave reception mode is selected, the TRX bit is set to “1”
(transmit) if the least significant bit (R/W bit) of the address data trans-
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RENESAS [ RENESAS TECHNOLOGY CORP ]
