MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
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2
(1) I C Data Shift Register
The I C data shift register (S0 : address 00F616) is an 8-bit shift
register to store receive data and write transmit data.
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0
I2 C address register
(S0D: address 00F716)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1 SAD0 RBW
When transmit data is written into this register, it is transferred to the
outside from bit 7 in synchronization with the SCL clock, and each
time one-bit data is output, the data of this register are shifted one bit
to the left. When data is received, it is input to this register from bit 0
in synchronization with the SCL clock, and each time one-bit data is
input, the data of this register are shifted one bit to the left.
Read/write bit
Slave address
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The I C data shift register is in a write enable status only when the
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2
ES0 bit of the I C control register (address 00F916) is “1.” The bit
Fig. 37. Structure of I C address register
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counter is reset by a write instruction to the I C data shift register.
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When both the ES0 bit and the MST bit of the I C status register
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(3) I C Clock Control Register
(address 00F816) are “1,” the SCL is output by a write instruction to
The I C clock control register (address 00FA16) is used to set ACK
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the I C data shift register. Reading data from the I C data shift regis-
ter is always enabled regardless of the ES0 bit value.
control, SCL mode and SCL frequency.
■ Bits 0 to 4: SCL frequency control bits (CCR0–CCR4)
These bits control the SCL frequency. Refer to Table 7.
■ Bit 5: SCL mode specification bit (FAST MODE)
This bit specifies the SCL mode. When this bit is set to “0,” the stan-
dard clock mode is set. When the bit is set to “1,” the high-speed
clock mode is set.
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Note: To write data into the I C data shift register after setting the
MST bit to “0” (slave mode), keep an interval of 8 machine
cycles or more.
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(2) I C Address Register
■ Bit 6: ACK bit (ACK BIT)
The I C address register (address 00F716) consists of a 7-bit slave
This bit sets the SDA status when an ACK clock✽ is generated. When
this bit is set to “0,” the ACK return mode is set and make SDA “L” at
the occurrence of an ACK clock. When the bit is set to “1,” the ACK
non-return mode is set. The SDA is held in the “H” status at the oc-
currence of an ACK clock.
address and a read/write bit. In the addressing mode, the slave ad-
dress written in this register is compared with the address data to be
received immediately after the START condition are detected.
■ Bit 0: Read/write bit (RBW)
Not used in the 7-bit addressing mode. In the 10-bit addressing mode,
However, when the slave address matches the address data in the
reception of address data at ACK BIT = “0,” the SDA is automatically
made “L” (ACK is returned). If there is a mismatch between the slave
address and the address data, the SDA is automatically made
“H”(ACK is not returned).
the first address data to be received is compared with the contents
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(SAD6 to SAD0 + RBW) of the I C address register.
The RBW bit is cleared to “0” automatically when the stop condition
is detected.
■ Bits 1 to 7: Slave address (SAD0–SAD6)
These bits store slave addresses. Regardless of the 7-bit address-
ing mode and the 10-bit addressing mode, the address data trans-
mitted from the master is compared with the contents of these bits.
✽ACK clock: Clock for acknowledgement
■ Bit 7: ACK clock bit (ACK)
This bit specifies a mode of acknowledgment which is an acknowl-
edgment response of data transmission. When this bit is set to “0,”
the no ACK clock mode is set. In this case, no ACK clock occurs
after data transmission. When the bit is set to “1,” the ACK clock
mode is set and the master generates an ACK clock upon comple-
tion of each 1-byte data transmission.The device for transmitting
address data and control data releases the SDA at the occurrence of
an ACK clock (make SDA “H”) and receives the ACK bit generated
by the data receiving device.
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Note: Do not write data into the I C clock control register during
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transmitting. If data is written during transmitting, the I C clock
generator is reset, so that data cannot be transmitted nor-
mally.
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RENESAS [ RENESAS TECHNOLOGY CORP ]
