MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
(4) I C Control Register
2
7
0
The I C control register (address 00F916) controls data communica-
I2C clock control register
ACK FAST
BIT MODE
tion format.
ACK
CCR4 CCR3 CCR2 CCR1 CCR0
(S2 : address 00FA16
)
■ Bits 0 to 2: Bit counter (BC0–BC2)
These bits decide the number of bits for the next 1-byte data to be
transmitted. An interrupt request signal occurs immediately after the
number of bits specified with these bits are transmitted.
When a START condition is received, these bits become “0002” and
the address data is always transmitted and received in 8 bits.
SCL frequency
control bits
Refer to Table 7.
SCL mode
specification bit
0 : Standard clock
mode
1 : High-speed clock
mode
2
■ Bit 3: I C interface use enable bit (ES0)
2
This bit enables to use the multimaster I C BUS interface. When this
bit is set to “0,” the use disable status is provided, so the SDA and
the SCL become high-impedance. When the bit is set to “1,” use of
the interface is enabled.
ACK bit
0 : ACK is returned.
1 : ACK is not returned.
When ES0 = “0,” the following is performed.
ACK clock bit
0 : No ACK clock
1 : ACK clock
2
PIN = “1,” BB = “0” and AL = “0” are set (they are bits of the I C
•
status register at address 00F816 ).
2
Writing data to the I C data shift register (address 00F616) is dis-
•
2
Fig. 38. Structure of I C clock control register
abled.
■ Bit 4: Data format selection bit (ALS)
This bit decides whether or not to recognize slave addresses. When
this bit is set to “0,” the addressing format is selected, so that ad-
dress data is recognized. When a match is found between a slave
address and address data as a result of comparison or when a gen-
2
Table 7. Set values of I C clock control register and SCL
frequency
Setting value of
CCR4–CCR0
SCL frequency
(at φ = 4MHz, unit : kHz)
2
eral call (refer to “(5) I C Status Register,” bit 1) is received, trans-
Standard clock
mode
High-speed clock
mode
CCR4 CCR3 CCR2 CCR1 CCR0
mission processing can be performed. When this bit is set to “1,” the
free data format is selected, so that slave addresses are not recog-
nized.
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
0
0
1
1
0
0
1
0
1
0
1
0
1
0
Setting disabled
Setting disabled
Setting disabled
Setting disabled
Setting disabled
100
Setting disabled
Setting disabled
Setting disabled
333
■ Bit 5: Addressing format selection bit (10BIT SAD)
This bit selects a slave address specification format. When this bit is
set to “0,” the 7-bit addressing format is selected. In this case, only
250
2
the high-order 7 bits (slave address) of the I C address register (ad-
400(Note)
166
dress 00F716) are compared with address data. When this bit is set
2
83.3
to “1,” the 10-bit addressing format is selected, all the bits of the I C
address register are compared with address data.
500/CCR value
1000/CCR value
2
■ Bits 6 and 7: Connection control bits between I C-BUS interface
1
1
1
1
1
1
1
1
1
0
1
1
1
0
1
17.2
16.6
16.1
34.5
33.3
32.3
and ports (BSEL0, BSEL1)
These bits controls the connection between SCL and ports or SDA
and ports (refer to Figure 39).
Note: At 400 kHz in the high-speed clock mode, the duty is 40%.
In the other cases, the duty is 50%.
38
RENESAS [ RENESAS TECHNOLOGY CORP ]
