MITSUBISHI MICROCOMPUTERS
M37270MF-XXXSP
M37270EF-XXXSP, M37270EFSP
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER with CLOSED CAPTION DECODER
and ON-SCREEN DISPLAY CONTROLLER
2
2
Table 6. Multi-master I C-BUS interface functions
MULTI-MASTER I C-BUS INTERFACE
2
The multi-master I C-BUS interface is a circuit for serial communica-
Function
Item
2
tions conformed with the Philips I C-BUS data transfer format. This
2
In conformity with Philips I C-BUS
standard:
interface, having an arbitration lost detection function and a synchro-
10-bit addressing format
7-bit addressing format
High-speed clock mode
Standard clock mode
nous function, is useful for serial communications of the multi-mas-
ter.
Format
2
Figure 36 shows a block diagram of the multi-master I C-BUS inter-
2
face and Table 6 shows multi-master I C-BUS interface functions.
2
In conformity with Philips I C-BUS
standard:
Master transmission
Master reception
Slave transmission
Slave reception
2
2
This multi-master I C-BUS interface consists of the I C address reg-
2
2
2
ister, the I C data shift register, the I C clock control register, the I C
Communication mode
2
control register, the I C status register and other control circuits.
16.1 kHz to 400 kHz (at φ = 4 MHz)
SCL clock frequency
φ : System clock = f(XIN)/2
Note: We are not responsible for any third party’s infringement of
patent rights or other rights attributable to the use of the con-
2
trol function (bits 6 and 7 of the I C control register at address
2
00F916) for connections between the I C-BUS interface and
ports (SCL1, SCL2, SDA1, SDA2).
I2 C address register
b7
b0
Interrupt
generating
circuit
Interrupt
request signal
(IICIRQ)
SAD6 SAD5 SAD4 SAD3 SAD2 SAD1SAD0 RBW
S0D
Address comparator
I 2C data shift register
Serial
data
(SDA)
Noise
elimination
circuit
Data
control
circuit
b7
b0
b7
b0
S0
AL AAS AD0 LRB
MST TRX BB PIN
S1
I2C status
register
AL
circuit
Internal data bus
BB
circuit
Noise
elimination
circuit
Serial
Clock
control
circuit
b7
ACK
S2
b0
b7
BSEL1 BSEL0
b0
clock
(SCL)
FAST
MODE
ACK
BIT
10BIT
SAD
CCR4 CCR3 CCR2 CCR1 CCR0
ALS ES0 BC2 BC1 BC0
S1D I2C clock control register
System clock ( φ )
I2C clock control register
Clock division
Bit counter
2
Fig. 36. Block diagram of multi-master I C-BUS interface
36
RENESAS [ RENESAS TECHNOLOGY CORP ]
