DMAC
9.3 Functional Description of the DMAC
9
Table 9.3.6 DMA Transfer Request Sources and Generation Timings on DMA5
REQSL5
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
Software start or one DMA7
transfer completed
When any data is written to the DMA5 Software Request Generation Register
(software start) or when one DMA7 transfer is completed (cascade mode)
When all DMA0 transfers are completed (cascade mode)
0
1
1
0
All DMA0 transfers completed
Serial I/O2 (reception completed) When serial I/O2 reception is completed
1
1
Extended DMA5 transfer request The source selected by the DMA5 Channel Control Register 1 (DM5CNT1)
source selected
REQESEL5 bits (see below)
REQESEL5 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When MJT TIN20 input signal is generated
MJT TOU0_0 interrupt source
0000
0001
0010
MJT (TIN20 input signal)
MJT (TOU0_0irq)
MJT (TOU2_7irq)
MJT TOU2_7 interrupt source
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
Table 9.3.7 DMA Transfer Request Sources and Generation Timings on DMA6
REQSL6
DMA Transfer Request Source
Software start
DMA Transfer Request Generation Timing
0
0
1
0
1
0
When any data is written to the DMA4 Software Request Generation Register
Serial I/O1 (transmit buffer empty) When serial I/O1 transmit buffer is empty
MJT (TIN1 input signal) When MJT TIN1 input signal is generated
Extended DMA6 transfer request The source selected by the DMA6 Channel Control Register 1 (DM6CNT1)
1
1
source selected
REQESEL6 bits (see below)
REQESEL6 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When one DMA5 transfer is completed (cascade mode)
MJT TOU0_1 interrupt source
0000
0001
0010
One DMA5 transfer completed
MJT (TOU0_1irq)
Serial I/O1 (reception completed) When serial I/O1 reception is completed
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-30
RENESAS [ RENESAS TECHNOLOGY CORP ]
