DMAC
9.3 Functional Description of the DMAC
9
Table 9.3.10 DMA Transfer Request Sources and Generation Timings on DMA9
REQSL9
DMA Transfer Request Source
Software start
DMA Transfer Request Generation Timing
0
0
1
0
1
0
When any data is written to the DMA9 Software Request Generation Register
Serial I/O3 (transmit buffer empty) When serial I/O3 transmit buffer is empty
MJT (TIN8 input signal) When MJT TIN8 input signal is generated
Extended DMA9 transfer request The source selected by the DMA9 Channel Control Register 1 (DM9CNT1)
1
1
source selected
REQESEL9 bits (see below)
REQESEL9 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When one DMA8 transfer is completed (cascade mode)
MJT TOU0_7 interrupt source
0000
0001
0010
One DMA8 transfer completed
MJT (TOU0_7irq)
A-D0 conversion completed
When A-D0 conversion is completed
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-32
RENESAS [ RENESAS TECHNOLOGY CORP ]
