DMAC
9.3 Functional Description of the DMAC
9
Table 9.3.8 DMA Transfer Request Sources and Generation Timings on DMA7
REQSL7
DMA Transfer Request Source
Software start
DMA Transfer Request Generation Timing
0
0
1
0
1
0
When any data is written to the DMA7 Software Request Generation Register
Serial I/O2 (transmit buffer empty) When serial I/O2 transmit buffer is empty
MJT (TIN2 input signal) When MJT TIN2 input signal is generated
Extended DMA7 transfer request The source selected by the DMA7 Channel Control Register 1 (DM7CNT1)
1
1
source selected
REQESEL7 bits (see below)
REQESEL7 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When one DMA6 transfer is completed (cascade mode)
MJT TOU0_2 interrupt source
0000
0001
0010
One DMA6 transfer completed
MJT (TOU0_2irq)
Serial I/O3 (reception completed) When serial I/O3 reception is completed
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
Table 9.3.9 DMA Transfer Request Sources and Generation Timings on DMA8
REQSL8
DMA Transfer Request Source
DMA Transfer Request Generation Timing
0
0
1
0
1
0
Software start
When any data is written to the DMA8 Software Request Generation Register
When MJT input event bus 0 signal is generated
MJT (input event bus 0)
Serial I/O3 (reception completed) When serial I/O3 reception is completed
1
1
Extended DMA8 transfer request The source selected by the DMA8 Channel Control Register 1 (DM8CNT1)
source selected
REQESEL8 bits (see below)
REQESEL8 DMA Transfer Request Source
DMA Transfer Request Generation Timing
When MJT TIN7 input signal is generated
MJT TOU0_6 interrupt source
0000
0001
0010
MJT (TIN7 input signal)
MJT (TOU0_6irq)
One DMA7 transfer completed
When one DMA7 transfer is completed (cascade mode)
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-31
RENESAS [ RENESAS TECHNOLOGY CORP ]
