DMAC
9.3 Functional Description of the DMAC
9
9.3 Functional Description of the DMAC
9.3.1 DMA Transfer Request Sources
For each DMA channel (channels 0–9), DMA transfer can be requested from two or more sources. There are
various causes or sources of DMA transfer request, so that DMA transfer can be started by a request from some
internal peripheral I/O, started in software by a program, or can be started upon completion of one transfer or all
transfers on another DMA channel (cascade mode).
The causes or sources of DMA transfer requests are selected using the transfer request source select bits
REQSLn on each channel (DMAn Channel Control Register 0 bits 2–3) or the extended transfer request source
select bits REQESELn (DMAn Channel Control Register 1 bits 12–15). The tables below list the causes or
sources of DMA transfer requests on each channel.
Table 9.3.1 DMA Transfer Request Sources and Generation Timings on DMA0
REQSL0
DMA Transfer Request Source
Software start or one DMA2
transfer completed
DMA Transfer Request Generation Timing
0
0
When any data is written to the DMA0 Software Request Generation Register
(software start) or when one DMA2 transfer is completed (cascade mode)
When A-D0 conversion is completed
0
1
1
0
A-D0 conversion completed
MJT (TIO8_udf)
When MJT TIO8 underflows
1
1
Extended DMA0 transfer request The source selected by the DMA0 Channel Control Register 1 (DM0CNT1)
source selected
REQESEL0 bits (see below)
REQESEL0 DMA Transfer Request Source
DMA Transfer Request Generation Timing
0000
0001
0010
MJT (input event bus 2)
MJT (TID0_udf/ovf)
When MJT input event bus 2 signal is generated
When MJT TID0 underflow/overflow occurs
CAN (CAN0_S0/S15)
When CAN0 slot 0 transmission failed or slot 15 transmission reception finished
0011
0100
0101
0110
0111
1000
1001
MJT (input event bus 1)
MJT (input event bus 3)
MJT (output event bus 2)
MJT (output event bus 3)
A-D0 conversion completed
MJT (TIN0 input signal)
MJT (TIO8_udf)
When MJT input event bus 1 signal is generated
When MJT input event bus 3 signal is generated
When MJT output event bus 2 signal is generated
When MJT output event bus 3 signal is generated
When A-D0 conversion is completed
When MJT TIN0 input signal is generated
When MJT TIO8 underflow occurs
1010
|
Settings inhibited
–
1111
32180 Group User’s Manual (Rev.1.0)
9-27
RENESAS [ RENESAS TECHNOLOGY CORP ]
